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| MPU wakeup latency to avoid I2C FIFO overruns |
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| Paul Walmsley <paul@pwsan.com>, 12 May 2009 |
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| Given: |
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Unit conversions: |
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| I2C bus clock rate | 2600 | KHz |
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8 | bits/byte |
| FIFO depth | 8 | bytes |
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1000 | Hz per KHz |
| FIFO threshold | 4 | bytes |
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1000000 | microseconds per second |
| Channel capacity | 1 | bit/Hz |
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| Derived: |
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| I2C bit rate | 2600000 | bits/second |
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| I2C byte rate | 325000 | bytes/second |
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| FIFO remaining capacity after interrupt | 4 | bytes |
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| FIFO remainder fill time | 12.31 | microseconds |
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| Parameter to pass to MPU wakeup lat | 12 | microseconds |
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