8(%ti,omap2430-sdpti,omap2430ti,omap2&7TI OMAP2430 SDPchosenaliases=/ocp/serial@4806a000E/ocp/serial@4806c000M/ocp/serial@4806e000U/ocp/i2c@48070000Z/ocp/i2c@48072000memory_memorykcpuscpuarm,arm1136jf-s_cpupmuarm,arm1136-pmuosocti,omap-inframpu ti,omap2-mpuzmpuocp simple-buszl3_mainaes@480a6000 ti,omap2-aeszaeskH `P  txrx1w@480b2000ti,omap2420-1wzhdq1wkH o:interrupt-controller@1ti,omap2-intc`kHdma-controller@48056000"ti,omap2430-sdmati,omap2420-sdmazdmakH`o  @i2c@48070000ti,omap2430-i2czi2c1kHo8txrxi2c@48072000ti,omap2430-i2czi2c2kH o9txrxtwl@48kHo ti,twl4030rtcti,twl4030-rtco bciti,twl4030-bcio watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 '8 regulator-vdacti,twl4030-vdac w@8w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1 :80regulator-vmmc2ti,twl4030-vmmc2 :80regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2 w@8w@regulator-vsimti,twl4030-vsim w@8-gpioti,twl4030-gpioP`twl4030-usbti,twl4030-usbo lzpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonokeypadti,twl4030-keypadomadcti,twl4030-madcomcspi@48098000ti,omap2-mcspizmcspi1kH oA@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3mcspi@4809a000ti,omap2-mcspizmcspi2kH oB +,-.tx0rx0tx1rx1rng@480a0000 ti,omap2-rngzrngkH Po4sham@480a4000ti,omap2-shamzshamkH @do3 rxserial@4806a000ti,omap2-uartzuart1kH oH12txrxlserial@4806c000ti,omap2-uartzuart2kHoI34txrxlserial@4806e000ti,omap2-uartzuart3kHoJ56txrxltimer@4802a000ti,omap2420-timerkHo&ztimer2timer@48078000ti,omap2420-timerkHo'ztimer3timer@4807a000ti,omap2420-timerkHo(ztimer4timer@4807c000ti,omap2420-timerkHo)ztimer5timer@4807e000ti,omap2420-timerkHo*ztimer6timer@48080000ti,omap2420-timerkHo+ztimer7timer@48082000ti,omap2420-timerkH o,ztimer8timer@48084000ti,omap2420-timerkH@o-ztimer9timer@48086000ti,omap2420-timerkH`o.ztimer10timer@48088000ti,omap2420-timerkHo/ztimer11timer@4808a000ti,omap2420-timerkHo0ztimer12dss@48050000 ti,omap2-dsskH disabled zdss_coredispc@48050400ti,omap2-dispckHo zdss_dispcencoder@48050800ti,omap2-rfbikH disabled zdss_rfbiencoder@48050c00ti,omap2-venckH  disabled zdss_vencprcm@49006000ti,omap2-prcmkI`clocksfunc_32k_ck  fixed-clock33secure_32k_ck  fixed-clockvirt_12m_ck  fixed-clock  virt_13m_ck  fixed-clock]@virt_19200000_ck  fixed-clock$virt_26m_ck  fixed-clockaplls_clkin_ck  ti,mux-clock k@  aplls_clkin_x2_ck fixed-factor-clock ,7  osc_ck  ti,mux-clock k`A  sys_ck ti,divider-clock Xk`A  alt_ck  fixed-clock7mcbsp_clks  fixed-clockLLdpll_ck ti,omap2-dpll-core-clock k@apll96_ck ti,omap2-apll-clock cs k0 apll54_ck ti,omap2-apll-clock c s7 k0 func_54m_ck  ti,mux-clockk@core_ck fixed-factor-clock,7func_96m_ck  ti,mux-clockk@apll96_d2_ck fixed-factor-clock,7func_48m_ck  ti,mux-clockk@func_12m_ck fixed-factor-clock,7MMsys_clkout_src_gate  ti,composite-no-wait-gate-clockkpsys_clkout_src_mux ti,composite-mux-clock kpsys_clkout_src ti,composite-clocksys_clkout ti,divider-clockX@kpemul_ck ti,gate-clockkxWWmpu_ck ti,divider-clockXk@Adsp_gate_fck ti,composite-gate-clockkdsp_div_fck ti,composite-divider-clockk@XAdsp_fck ti,composite-clockNNcore_l3_ck ti,divider-clockXk@Agfx_3d_gate_fck ti,composite-gate-clockkgfx_3d_div_fck ti,composite-divider-clockXk@Agfx_3d_fck ti,composite-clockgfx_2d_gate_fck ti,composite-gate-clockkgfx_2d_div_fck ti,composite-divider-clockXk@A  gfx_2d_fck ti,composite-clock gfx_ick ti,wait-gate-clockkSSl4_ck ti,divider-clockXk@A!!dss_ick !ti,omap3-no-wait-interface-clock!kaadss1_gate_fck  ti,composite-no-wait-gate-clockk++core_d2_ck fixed-factor-clock,7""core_d3_ck fixed-factor-clock,7##core_d4_ck fixed-factor-clock,7$$core_d5_ck fixed-factor-clock,7%%core_d6_ck fixed-factor-clock,7&&dummy_ck  fixed-clockcore_d8_ck fixed-factor-clock,7''core_d9_ck fixed-factor-clock,7 ((core_d12_ck fixed-factor-clock,7 ))core_d16_ck fixed-factor-clock,7**dss1_mux_fck ti,composite-mux-clock, "#$%&'()*k@,,dss1_fck ti,composite-clock+,dss2_gate_fck  ti,composite-no-wait-gate-clockk--dss2_mux_fck ti,composite-mux-clock  k@..dss2_fck ti,composite-clock-.dss_54m_fck ti,wait-gate-clockkbbssi_ssr_sst_gate_fck ti,composite-gate-clockk//ssi_ssr_sst_div_fck ti,composite-divider-clockk@XA00ssi_ssr_sst_fck ti,composite-clock/0usb_l4_gate_ick ti,composite-interface-clockk11usb_l4_div_ick ti,composite-divider-clockk@22usb_l4_ick ti,composite-clock12ssi_l4_ick ti,omap3-interface-clock!kccgpt1_ick ti,omap3-interface-clock kXXgpt1_gate_fck ti,composite-gate-clock3k44gpt1_mux_fck ti,composite-mux-clock 3 k@55gpt1_fck ti,composite-clock45gpt2_ick ti,omap3-interface-clock!kddgpt2_gate_fck ti,composite-gate-clock3k66gpt2_mux_fck ti,composite-mux-clock 3 kD77gpt2_fck ti,composite-clock67gpt3_ick ti,omap3-interface-clock!keegpt3_gate_fck ti,composite-gate-clock3k88gpt3_mux_fck ti,composite-mux-clock 3 kD99gpt3_fck ti,composite-clock89gpt4_ick ti,omap3-interface-clock!kffgpt4_gate_fck ti,composite-gate-clock3k::gpt4_mux_fck ti,composite-mux-clock 3 kD;;gpt4_fck ti,composite-clock:;gpt5_ick ti,omap3-interface-clock!kgggpt5_gate_fck ti,composite-gate-clock3k<<gpt5_mux_fck ti,composite-mux-clock 3 kD==gpt5_fck ti,composite-clock<=gpt6_ick ti,omap3-interface-clock!khhgpt6_gate_fck ti,composite-gate-clock3k>>gpt6_mux_fck ti,composite-mux-clock 3  kD??gpt6_fck ti,composite-clock>?gpt7_ick ti,omap3-interface-clock! kiigpt7_gate_fck ti,composite-gate-clock3 k@@gpt7_mux_fck ti,composite-mux-clock 3  kDAAgpt7_fck ti,composite-clock@Agpt8_ick ti,omap3-interface-clock! kjjgpt8_gate_fck ti,composite-gate-clock3 kBBgpt8_mux_fck ti,composite-mux-clock 3 kDCCgpt8_fck ti,composite-clockBCgpt9_ick ti,omap3-interface-clock! kkkgpt9_gate_fck ti,composite-gate-clock3 kDDgpt9_mux_fck ti,composite-mux-clock 3 kDEEgpt9_fck ti,composite-clockDEgpt10_ick ti,omap3-interface-clock! kllgpt10_gate_fck ti,composite-gate-clock3 kFFgpt10_mux_fck ti,composite-mux-clock 3 kDGGgpt10_fck ti,composite-clockFGgpt11_ick ti,omap3-interface-clock! kmmgpt11_gate_fck ti,composite-gate-clock3 kHHgpt11_mux_fck ti,composite-mux-clock 3 kDIIgpt11_fck ti,composite-clockHIgpt12_ick ti,omap3-interface-clock!knngpt12_gate_fck ti,composite-gate-clock3kJJgpt12_mux_fck ti,composite-mux-clock 3 kDKKgpt12_fck ti,composite-clockJKmcbsp1_ick ti,omap3-interface-clock!koomcbsp1_gate_fck ti,composite-gate-clockLkmcbsp2_ick ti,omap3-interface-clock!kppmcbsp2_gate_fck ti,composite-gate-clockLkmcspi1_ick ti,omap3-interface-clock!kttmcspi1_fck ti,wait-gate-clockkuumcspi2_ick ti,omap3-interface-clock!kvvmcspi2_fck ti,wait-gate-clockkwwuart1_ick ti,omap3-interface-clock!kzzuart1_fck ti,wait-gate-clockk{{uart2_ick ti,omap3-interface-clock!k||uart2_fck ti,wait-gate-clockk}}uart3_ick ti,omap3-interface-clock!k~~uart3_fck ti,wait-gate-clockkgpios_ick ti,omap3-interface-clock kYYgpios_fck ti,wait-gate-clock3kZZmpu_wdt_ick ti,omap3-interface-clock k[[mpu_wdt_fck ti,wait-gate-clock3k\\sync_32k_ick ti,omap3-interface-clock k]]wdt1_ick ti,omap3-interface-clock k^^omapctrl_ick ti,omap3-interface-clock k__cam_fck ti,gate-clockkTTcam_ick !ti,omap3-no-wait-interface-clock!kmailboxes_ick ti,omap3-interface-clock!kwdt4_ick ti,omap3-interface-clock!kwdt4_fck ti,wait-gate-clock3kmspro_ick ti,omap3-interface-clock!kmspro_fck ti,wait-gate-clockkfac_ick ti,omap3-interface-clock!kfac_fck ti,wait-gate-clockMkhdq_ick ti,omap3-interface-clock!khdq_fck ti,wait-gate-clockMki2c1_ick ti,omap3-interface-clock!ki2c2_ick ti,omap3-interface-clock!kgpmc_fck ti,fixed-factor-clockk8sdma_fck fixed-factor-clock,7sdma_ick ti,fixed-factor-clockk8sdrc_ick ti,fixed-factor-clockk8des_ick ti,omap3-interface-clock!ksha_ick ti,omap3-interface-clock!krng_ick ti,omap3-interface-clock!kaes_ick ti,omap3-interface-clock!kpka_ick ti,omap3-interface-clock!kusb_fck ti,wait-gate-clockkUUiva2_1_gate_ick ti,composite-gate-clockNkOOiva2_1_div_ick ti,composite-divider-clockNXk@APPiva2_1_ick ti,composite-clockOPmdm_gate_ick ti,composite-interface-clockk QQmdm_div_ick ti,composite-divider-clockk @( RRmdm_ick ti,composite-clockQRmdm_osc_ck ti,omap3-interface-clock k mcbsp3_ick ti,omap3-interface-clock!kqqmcbsp3_gate_fck ti,composite-gate-clockLkmcbsp4_ick ti,omap3-interface-clock!krrmcbsp4_gate_fck ti,composite-gate-clockLkmcbsp5_ick ti,omap3-interface-clock!kssmcbsp5_gate_fck ti,composite-gate-clockLkmcspi3_ick ti,omap3-interface-clock! kxxmcspi3_fck ti,wait-gate-clock kyyicr_ick ti,omap3-interface-clock k``i2chs1_fck ti,omap2430-interface-clockki2chs2_fck ti,omap2430-interface-clockkusbhs_ick ti,omap3-interface-clockkVVmmchs1_ick ti,omap3-interface-clock!kmmchs1_fck ti,wait-gate-clockkmmchs2_ick ti,omap3-interface-clock!kmmchs2_fck ti,wait-gate-clockkgpio5_ick ti,omap3-interface-clock! kgpio5_fck ti,wait-gate-clock3 kmdm_intc_ick ti,omap3-interface-clock! kmmchsdb1_fck ti,wait-gate-clock3kmmchsdb2_fck ti,wait-gate-clock3kclockdomainsgfx_clkdmti,clockdomainScore_l3_clkdmti,clockdomain TUVwkup_clkdmti,clockdomain,WXYZ[\]^_`dss_clkdmti,clockdomainabcore_l4_clkdmti,clockdomaincdefghijklmnopqrstuvwxyz{|}~mdm_clkdmti,clockdomainscrm@49002000ti,omap2-scrmkI clocksmcbsp1_mux_fck ti,composite-mux-clockLktmcbsp1_fck ti,composite-clockmcbsp2_mux_fck ti,composite-mux-clockLktmcbsp2_fck ti,composite-clockmcbsp3_mux_fck ti,composite-mux-clockLkmcbsp3_fck ti,composite-clockmcbsp4_mux_fck ti,composite-mux-clockLkmcbsp4_fck ti,composite-clockmcbsp5_mux_fck ti,composite-mux-clockLkmcbsp5_fck ti,composite-clockclockdomainscounter@49020000ti,omap-counter32kkI  zcounter_32kpinmux@49002030#ti,omap2430-padconfpinctrl-singlekI 0T?tisyscon@49002270sysconkI"p@pbias_regulatorti,pbias-omapk0pbias_mmc_omap2430pbias_mmc_omap2430 w@8-gpio@4900c000ti,omap2-gpiokIozgpio1&`Pgpio@4900e000ti,omap2-gpiokIozgpio2&`Pgpio@49010000ti,omap2-gpiokIozgpio3&`Pgpio@49012000ti,omap2-gpiokI o zgpio4&`Pgpio@480b6000ti,omap2-gpiokH `o!zgpio5`Pgpmc@6e000000ti,omap2430-gpmckno8Dzgpmcethernet@gpmcsmsc,lan91c94&o kVamcbsp@48074000ti,omap2430-mcbspkH@smpuo@;<=}commontxrxrx_overflowzmcbsp1 txrx disabledmcbsp@48076000ti,omap2430-mcbspkH`smpu o>? }commontxrxzmcbsp2!"txrx disabledmcbsp@4808c000ti,omap2430-mcbspkHsmpu oYZ }commontxrxzmcbsp3txrx disabledmcbsp@4808e000ti,omap2430-mcbspkHsmpu o67 }commontxrxzmcbsp4txrx disabledmcbsp@48096000ti,omap2430-mcbspkH `smpu oQR }commontxrxzmcbsp5txrx disabledmmc@4809c000ti,omap2-hsmmckH oSzmmc1=>txrxmmc@480b4000ti,omap2-hsmmckH @oVzmmc2/0txrxmailbox@48094000ti,omap2-mailboxkH @ozmailboxtimer@49018000ti,omap2420-timerkIo%ztimer1mcspi@480b8000ti,omap2-mcspizmcspi3kH o[ tx0rx0tx1rx1usb_otg_hs@480ac000ti,omap2-musb zusb_otg_hskH o]wdt@49016000 ti,omap2-wdt zwd_timer2kI` #address-cells#size-cellscompatibleinterrupt-parentmodelserial0serial1serial2i2c0i2c1device_typereginterruptsti,hwmodsrangesdmasdma-namesinterrupt-controller#interrupt-cellsti,intc-sizelinux,phandle#dma-cells#dma-channels#dma-requestsclock-frequencybci3v1-supplyregulator-min-microvoltregulator-max-microvoltgpio-controller#gpio-cellsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsti,timer-dspti,timer-pwmstatus#clock-cellsclocksti,bit-shiftclock-multclock-divti,index-starts-at-oneti,max-divti,idlest-shiftti,clock-frequencyti,index-power-of-twoti,dividersti,clock-divti,autoidle-shiftti,clock-multpinctrl-single,register-widthpinctrl-single,function-masksysconregulator-nameti,gpio-always-ongpmc,num-csgpmc,num-waitpinsbank-widthgpmc,mux-add-datareg-namesinterrupt-namesti,buffer-sizeti,dual-voltpbias-supplyvmmc-supplybus-widthti,mbox-num-usersti,mbox-num-fifosti,timer-alwon