8(UT!ti,am3517-evmti,am3517ti,omap3&&7TI AM3517 EVM (AM3517/05 TMDSEVM3517)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@4809e000memorylmemoryxcpuscpu@0arm,cortex-a8lcpux|cpupmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp simple-busxh l3_mainaes@480c5000 ti,omap3-aesaesxH PPprm@48306000 ti,omap3-prmxH0`@clocksvirt_16_8m_ck fixed-clockYosc_sys_ck ti,mux-clock|x @  sys_ckti,divider-clock| xpsys_clkout1ti,gate-clock| x pdpll3_x2_ckfixed-factor-clock| %dpll3_m2x2_ckfixed-factor-clock| %  dpll4_x2_ckfixed-factor-clock| %corex2_fckfixed-factor-clock| %wkup_l4_ickfixed-factor-clock|%@@corex2_d3_fckfixed-factor-clock|%aacorex2_d5_fckfixed-factor-clock|%bbclockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock00virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ckti,omap3-dpll-per-clock|x D 0  dpll4_m2_ckti,divider-clock| ?x Hdpll4_m2x2_mul_ckfixed-factor-clock|%dpll4_m2x2_ckti,gate-clock|x /omap_96m_alwon_fckfixed-factor-clock|%dpll3_ckti,omap3-dpll-core-clock|x @ 0  dpll3_m3_ckti,divider-clock| x@dpll3_m3x2_mul_ckfixed-factor-clock|%dpll3_m3x2_ckti,gate-clock| x /emu_core_alwon_ckfixed-factor-clock|%TTsys_altclk fixed-clockmcbsp_clks fixed-clock77dpll3_m2_ckti,divider-clock| x @  core_ckfixed-factor-clock| %dpll1_fckti,divider-clock|x @dpll1_ckti,omap3-dpll-clock|x  $ @ 4dpll1_x2_ckfixed-factor-clock|%dpll1_x2m2_ckti,divider-clock|x D,,cm_96m_fckfixed-factor-clock|%omap_96m_fck ti,mux-clock|x @55dpll4_m3_ckti,divider-clock|  x@dpll4_m3x2_mul_ckfixed-factor-clock|%dpll4_m3x2_ckti,gate-clock|x /omap_54m_fck ti,mux-clock|x @((cm_96m_d2_fckfixed-factor-clock|%omap_48m_fck ti,mux-clock|x @  omap_12m_fckfixed-factor-clock| %99dpll4_m4_ckti,divider-clock|  x@!!dpll4_m4x2_mul_ckti,fixed-factor-clock|!ES`""dpll4_m4x2_ckti,gate-clock|"x /`ffdpll4_m5_ckti,divider-clock| ?x@##dpll4_m5x2_mul_ckti,fixed-factor-clock|#ES`$$dpll4_m5x2_ckti,gate-clock|$x /dpll4_m6_ckti,divider-clock| ?x@%%dpll4_m6x2_mul_ckfixed-factor-clock|%%&&dpll4_m6x2_ckti,gate-clock|&x /''emu_per_alwon_ckfixed-factor-clock|'%UUclkout2_src_gate_ck ti,composite-no-wait-gate-clock|x p))clkout2_src_mux_ckti,composite-mux-clock|(x p**clkout2_src_ckti,composite-clock|)*++sys_clkout2ti,divider-clock|+@x psmpu_ckfixed-factor-clock|,%--arm_fckti,divider-clock|-x $emu_mpu_alwon_ckfixed-factor-clock|-%VVl3_ickti,divider-clock|x @..l4_ickti,divider-clock|.x @//rm_ickti,divider-clock|/x @gpt10_gate_fckti,composite-gate-clock| x 11gpt10_mux_fckti,composite-mux-clock|0x @22gpt10_fckti,composite-clock|12gpt11_gate_fckti,composite-gate-clock| x 33gpt11_mux_fckti,composite-mux-clock|0x @44gpt11_fckti,composite-clock|34core_96m_fckfixed-factor-clock|5%66mmchs2_fckti,wait-gate-clock|6x mmchs1_fckti,wait-gate-clock|6x i2c3_fckti,wait-gate-clock|6x i2c2_fckti,wait-gate-clock|6x i2c1_fckti,wait-gate-clock|6x mcbsp5_gate_fckti,composite-gate-clock|7 x mcbsp1_gate_fckti,composite-gate-clock|7 x core_48m_fckfixed-factor-clock| %88mcspi4_fckti,wait-gate-clock|8x mcspi3_fckti,wait-gate-clock|8x mcspi2_fckti,wait-gate-clock|8x mcspi1_fckti,wait-gate-clock|8x uart2_fckti,wait-gate-clock|8x uart1_fckti,wait-gate-clock|8x  core_12m_fckfixed-factor-clock|9%::hdq_fckti,wait-gate-clock|:x core_l3_ickfixed-factor-clock|.%;;sdrc_ickti,wait-gate-clock|;x gggpmc_fckfixed-factor-clock|;%core_l4_ickfixed-factor-clock|/%<<mmchs2_ickti,omap3-interface-clock|<x mmchs1_ickti,omap3-interface-clock|<x hdq_ickti,omap3-interface-clock|<x mcspi4_ickti,omap3-interface-clock|<x mcspi3_ickti,omap3-interface-clock|<x mcspi2_ickti,omap3-interface-clock|<x mcspi1_ickti,omap3-interface-clock|<x i2c3_ickti,omap3-interface-clock|<x i2c2_ickti,omap3-interface-clock|<x i2c1_ickti,omap3-interface-clock|<x uart2_ickti,omap3-interface-clock|<x uart1_ickti,omap3-interface-clock|<x  gpt11_ickti,omap3-interface-clock|<x  gpt10_ickti,omap3-interface-clock|<x  mcbsp5_ickti,omap3-interface-clock|<x  mcbsp1_ickti,omap3-interface-clock|<x  omapctrl_ickti,omap3-interface-clock|<x dss_tv_fckti,gate-clock|(xdss_96m_fckti,gate-clock|5xdss2_alwon_fckti,gate-clock|xdummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock|x ==gpt1_mux_fckti,composite-mux-clock|0x @>>gpt1_fckti,composite-clock|=>aes2_ickti,omap3-interface-clock|<x wkup_32k_fckfixed-factor-clock|0%??gpio1_dbckti,gate-clock|?x sha12_ickti,omap3-interface-clock|<x wdt2_fckti,wait-gate-clock|?x wdt2_ickti,omap3-interface-clock|@x wdt1_ickti,omap3-interface-clock|@x gpio1_ickti,omap3-interface-clock|@x omap_32ksync_ickti,omap3-interface-clock|@x gpt12_ickti,omap3-interface-clock|@x gpt1_ickti,omap3-interface-clock|@x per_96m_fckfixed-factor-clock|%per_48m_fckfixed-factor-clock| %AAuart3_fckti,wait-gate-clock|Ax nngpt2_gate_fckti,composite-gate-clock|xBBgpt2_mux_fckti,composite-mux-clock|0x@CCgpt2_fckti,composite-clock|BCgpt3_gate_fckti,composite-gate-clock|xDDgpt3_mux_fckti,composite-mux-clock|0x@EEgpt3_fckti,composite-clock|DEgpt4_gate_fckti,composite-gate-clock|xFFgpt4_mux_fckti,composite-mux-clock|0x@GGgpt4_fckti,composite-clock|FGgpt5_gate_fckti,composite-gate-clock|xHHgpt5_mux_fckti,composite-mux-clock|0x@IIgpt5_fckti,composite-clock|HIgpt6_gate_fckti,composite-gate-clock|xJJgpt6_mux_fckti,composite-mux-clock|0x@KKgpt6_fckti,composite-clock|JKgpt7_gate_fckti,composite-gate-clock|xLLgpt7_mux_fckti,composite-mux-clock|0x@MMgpt7_fckti,composite-clock|LMgpt8_gate_fckti,composite-gate-clock| xNNgpt8_mux_fckti,composite-mux-clock|0x@OOgpt8_fckti,composite-clock|NOgpt9_gate_fckti,composite-gate-clock| xPPgpt9_mux_fckti,composite-mux-clock|0x@QQgpt9_fckti,composite-clock|PQper_32k_alwon_fckfixed-factor-clock|0%RRgpio6_dbckti,gate-clock|Rxoogpio5_dbckti,gate-clock|Rxppgpio4_dbckti,gate-clock|Rxqqgpio3_dbckti,gate-clock|Rxrrgpio2_dbckti,gate-clock|Rx sswdt3_fckti,wait-gate-clock|Rx ttper_l4_ickfixed-factor-clock|/%SSgpio6_ickti,omap3-interface-clock|Sxuugpio5_ickti,omap3-interface-clock|Sxvvgpio4_ickti,omap3-interface-clock|Sxwwgpio3_ickti,omap3-interface-clock|Sxxxgpio2_ickti,omap3-interface-clock|Sx yywdt3_ickti,omap3-interface-clock|Sx zzuart3_ickti,omap3-interface-clock|Sx {{uart4_ickti,omap3-interface-clock|Sx||gpt9_ickti,omap3-interface-clock|Sx }}gpt8_ickti,omap3-interface-clock|Sx ~~gpt7_ickti,omap3-interface-clock|Sxgpt6_ickti,omap3-interface-clock|Sxgpt5_ickti,omap3-interface-clock|Sxgpt4_ickti,omap3-interface-clock|Sxgpt3_ickti,omap3-interface-clock|Sxgpt2_ickti,omap3-interface-clock|Sxmcbsp2_ickti,omap3-interface-clock|Sxmcbsp3_ickti,omap3-interface-clock|Sxmcbsp4_ickti,omap3-interface-clock|Sxmcbsp2_gate_fckti,composite-gate-clock|7xmcbsp3_gate_fckti,composite-gate-clock|7xmcbsp4_gate_fckti,composite-gate-clock|7xemu_src_mux_ck ti,mux-clock|TUVx@WWemu_src_ckti,clkdm-gate-clock|WXXpclk_fckti,divider-clock|Xx@pclkx2_fckti,divider-clock|Xx@atclk_fckti,divider-clock|Xx@traceclk_src_fck ti,mux-clock|TUVx@YYtraceclk_fckti,divider-clock|Y x@secure_32k_fck fixed-clockZZgpt12_fckfixed-factor-clock|Z%wdt1_fckfixed-factor-clock|Z%ipss_ickti,am35xx-interface-clock|;x hhrmii_ck fixed-clockpclk_ck fixed-clockuart4_ick_am35xxti,omap3-interface-clock|<x uart4_fck_am35xxti,wait-gate-clock|8x dpll5_ckti,omap3-dpll-clock|x  $ L 4[[dpll5_m2_ckti,divider-clock|[x Peesgx_gate_fckti,composite-gate-clock|x cccore_d3_ckfixed-factor-clock|%\\core_d4_ckfixed-factor-clock|%]]core_d6_ckfixed-factor-clock|%^^omap_192m_alwon_fckfixed-factor-clock|%__core_d2_ckfixed-factor-clock|%``sgx_mux_fckti,composite-mux-clock |\]^_`abx @ddsgx_fckti,composite-clock|cdsgx_ickti,wait-gate-clock|.x cpefuse_fckti,gate-clock|x ts_fckti,gate-clock|0x usbtll_fckti,wait-gate-clock|ex usbtll_ickti,omap3-interface-clock|<x mmchs3_ickti,omap3-interface-clock|<x mmchs3_fckti,wait-gate-clock|6x dss1_alwon_fck_3430es2ti,dss-gate-clock|fx`dss_ick_3430es2ti,omap3-dss-interface-clock|/xusbhost_120m_fckti,gate-clock|exusbhost_48m_fckti,dss-gate-clock| xusbhost_ickti,omap3-dss-interface-clock|/xclockdomainscore_l3_clkdmti,clockdomain|ghijklmdpll3_clkdmti,clockdomain| dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainh|nopqrstuvwxyz{|}~emu_clkdmti,clockdomain|Xdpll4_clkdmti,clockdomain| wkup_clkdmti,clockdomain |dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|dpll5_clkdmti,clockdomain|[sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |scrm@48002000ti,omap3-scrmxH clocksmcbsp5_mux_fckti,composite-mux-clock|67xmcbsp5_fckti,composite-clock|mcbsp1_mux_fckti,composite-mux-clock|67xtmcbsp1_fckti,composite-clock|mcbsp2_mux_fckti,composite-mux-clock|7xtmcbsp2_fckti,composite-clock|mcbsp3_mux_fckti,composite-mux-clock|7xmcbsp3_fckti,composite-clock|mcbsp4_mux_fckti,composite-mux-clock|7xmcbsp4_fckti,composite-clock|emac_ickti,am35xx-gate-clock|hxiiemac_fckti,gate-clock|x vpfe_ickti,am35xx-gate-clock|hxjjvpfe_fckti,gate-clock|x hsotgusb_ick_am35xxti,am35xx-gate-clock|hxkkhsotgusb_fck_am35xxti,gate-clock|xllhecc_ckti,am35xx-gate-clock|xmmclockdomainscounter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap2-intc`xH dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `pinmux@48002030 ti,omap3-padconfpinctrl-singlexH 08pinmux@48002a00 ti,omap3-padconfpinctrl-singlexH*\tisyscon@48002270sysconxH"ppbias_regulatorti,pbias-omapx8pbias_mmc_omap2430?pbias_mmc_omap2430Nw@f-gpio@48310000ti,omap3-gpioxH1gpio1~gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5gpio@49058000ti,omap3-gpioxI"gpio6serial@4806a000ti,omap3-uartxH H12txrxuart1lserial@4806c000ti,omap3-uartxHI34txrxuart2lserial@49020000ti,omap3-uartxIJ56txrxuart3li2c@48070000 ti,omap3-i2cxH8txrxi2c1i2c@48072000 ti,omap3-i2cxH 9txrxi2c2i2c@48060000 ti,omap3-i2cxH=txrxi2c3mailbox@48094000ti,omap3-mailboxmailboxxH @ disabledspi@48098000ti,omap2-mcspixH Amcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH Bmcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrxmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuxH mmu_isp  disabledmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< 'commontxrx7mcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?'commontxrxsidetone7mcbsp2mcbsp2_sidetone!"txrx disabledmcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZ'commontxrxsidetone7mcbsp3mcbsp3_sidetonetxrx disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 'commontxrx7mcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR 'commontxrx7mcbsp5txrx disabledsham@480c3000ti,omap3-shamshamxH 0d1smartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH  disabledtimer@48318000ti,omap3430-timerxH1%timer1Ftimer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5Utimer@4903a000ti,omap3430-timerxI*timer6Utimer@4903c000ti,omap3430-timerxI+timer7Utimer@4903e000ti,omap3430-timerxI,timer8bUtimer@49040000ti,omap3430-timerxI-timer9btimer@48086000ti,omap3430-timerxH`.timer10btimer@48088000ti,omap3430-timerxH/timer11btimer@48304000ti,omap3430-timerxH0@_timer12Fousbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hsohci@48064400ti,ohci-omap3xHD&Lehci@48064800 ti,ehci-omapxHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcxnusb_otg_hs@480ab000ti,omap3-musbxH \]'mcdma usb_otg_hs dss@48050000 ti,omap3-dssxH disabled dss_core|fckdispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H protophypll disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH  disabled dss_venc|fckssi-controller@48058000 ti,omap3-ssissi disabledxHHsysgddG'gdd_mpussi-port@4805a000ti,omap3-ssi-portxHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portxHHtxrx&EFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hs disabledx\G'mcethernet@0x5c000000ti,am3517-emac davinci_emacokayx\CDEF ':ethernet@0x5c030000ti,davinci_mdio davinci_mdiookayx\LB@serial@4809e000ti,omap3-uartuart4 disabledxH T76txrxlvmmcregulator-fixed ?vmmc_fixedN2Zf2Z #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockinterrupt-controller#interrupt-cellsti,intc-size#dma-cells#dma-channels#dma-requestspinctrl-single,register-widthpinctrl-single,function-masksysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namesti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freq