38 (ti,omap3-beagleti,omap3&7TI OMAP3 BeagleBoardchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/connector@0 m/connector@1memoryvmemorycpuscpu@0arm,cortex-a8vcpucpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp simple-bush l3_mainaes@480c5000 ti,omap3-aesaesH PPprm@48306000 ti,omap3-prmH0`@clocksvirt_16_8m_ck fixed-clockY  osc_sys_ck ti,mux-clock  @  sys_ckti,divider-clock  p#sys_clkout1ti,gate-clock  p dpll3_x2_ckfixed-factor-clock :Edpll3_m2x2_ckfixed-factor-clock :Edpll4_x2_ckfixed-factor-clock :Ecorex2_fckfixed-factor-clock:Ewkup_l4_ickfixed-factor-clock:EAAcorex2_d3_fckfixed-factor-clock:Exxcorex2_d5_fckfixed-factor-clock:Eyyclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock11virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ckti,omap3-dpll-per-clock D 0  dpll4_m2_ckti,divider-clock ? H#dpll4_m2x2_mul_ckfixed-factor-clock:Edpll4_m2x2_ckti,gate-clock  Oomap_96m_alwon_fckfixed-factor-clock:Edpll3_ckti,omap3-dpll-core-clock @ 0  dpll3_m3_ckti,divider-clock  @#dpll3_m3x2_mul_ckfixed-factor-clock:Edpll3_m3x2_ckti,gate-clock  Oemu_core_alwon_ckfixed-factor-clock:EUUsys_altclk fixed-clockmcbsp_clks fixed-clock88dpll3_m2_ckti,divider-clock   @#  core_ckfixed-factor-clock :Edpll1_fckti,divider-clock  @#dpll1_ckti,omap3-dpll-clock  $ @ 4dpll1_x2_ckfixed-factor-clock:Edpll1_x2m2_ckti,divider-clock D#--cm_96m_fckfixed-factor-clock:Eomap_96m_fck ti,mux-clock  @66dpll4_m3_ckti,divider-clock   @#dpll4_m3x2_mul_ckfixed-factor-clock:Edpll4_m3x2_ckti,gate-clock  Oomap_54m_fck ti,mux-clock  @))cm_96m_d2_fckfixed-factor-clock:E  omap_48m_fck ti,mux-clock   @!!omap_12m_fckfixed-factor-clock!:E::dpll4_m4_ckti,divider-clock  @#""dpll4_m4x2_mul_ckti,fixed-factor-clock"es##dpll4_m4x2_ckti,gate-clock#  O||dpll4_m5_ckti,divider-clock ?@#$$dpll4_m5x2_mul_ckti,fixed-factor-clock$es%%dpll4_m5x2_ckti,gate-clock%  O]]dpll4_m6_ckti,divider-clock  ?@#&&dpll4_m6x2_mul_ckfixed-factor-clock&:E''dpll4_m6x2_ckti,gate-clock'  O((emu_per_alwon_ckfixed-factor-clock(:EVVclkout2_src_gate_ck ti,composite-no-wait-gate-clock  p**clkout2_src_mux_ckti,composite-mux-clock) p++clkout2_src_ckti,composite-clock*+,,sys_clkout2ti,divider-clock, @ pmpu_ckfixed-factor-clock-:E..arm_fckti,divider-clock. $emu_mpu_alwon_ckfixed-factor-clock.:EWWl3_ickti,divider-clock @#//l4_ickti,divider-clock/  @#00rm_ickti,divider-clock0  @#gpt10_gate_fckti,composite-gate-clock  22gpt10_mux_fckti,composite-mux-clock1  @33gpt10_fckti,composite-clock23gpt11_gate_fckti,composite-gate-clock  44gpt11_mux_fckti,composite-mux-clock1  @55gpt11_fckti,composite-clock45core_96m_fckfixed-factor-clock6:E77mmchs2_fckti,wait-gate-clock7  mmchs1_fckti,wait-gate-clock7  i2c3_fckti,wait-gate-clock7  i2c2_fckti,wait-gate-clock7  i2c1_fckti,wait-gate-clock7  mcbsp5_gate_fckti,composite-gate-clock8  mcbsp1_gate_fckti,composite-gate-clock8  core_48m_fckfixed-factor-clock!:E99mcspi4_fckti,wait-gate-clock9  mcspi3_fckti,wait-gate-clock9  mcspi2_fckti,wait-gate-clock9  mcspi1_fckti,wait-gate-clock9  uart2_fckti,wait-gate-clock9  uart1_fckti,wait-gate-clock9  core_12m_fckfixed-factor-clock::E;;hdq_fckti,wait-gate-clock;  core_l3_ickfixed-factor-clock/:E<<sdrc_ickti,wait-gate-clock<  }}gpmc_fckfixed-factor-clock<:Ecore_l4_ickfixed-factor-clock0:E==mmchs2_ickti,omap3-interface-clock=  mmchs1_ickti,omap3-interface-clock=  hdq_ickti,omap3-interface-clock=  mcspi4_ickti,omap3-interface-clock=  mcspi3_ickti,omap3-interface-clock=  mcspi2_ickti,omap3-interface-clock=  mcspi1_ickti,omap3-interface-clock=  i2c3_ickti,omap3-interface-clock=  i2c2_ickti,omap3-interface-clock=  i2c1_ickti,omap3-interface-clock=  uart2_ickti,omap3-interface-clock=  uart1_ickti,omap3-interface-clock=  gpt11_ickti,omap3-interface-clock=  gpt10_ickti,omap3-interface-clock=  mcbsp5_ickti,omap3-interface-clock=  mcbsp1_ickti,omap3-interface-clock=  omapctrl_ickti,omap3-interface-clock=  dss_tv_fckti,gate-clock) dss_96m_fckti,gate-clock6 dss2_alwon_fckti,gate-clock dummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock  >>gpt1_mux_fckti,composite-mux-clock1 @??gpt1_fckti,composite-clock>?aes2_ickti,omap3-interface-clock=  wkup_32k_fckfixed-factor-clock1:E@@gpio1_dbckti,gate-clock@  sha12_ickti,omap3-interface-clock=  wdt2_fckti,wait-gate-clock@  wdt2_ickti,omap3-interface-clockA  wdt1_ickti,omap3-interface-clockA  gpio1_ickti,omap3-interface-clockA  omap_32ksync_ickti,omap3-interface-clockA  gpt12_ickti,omap3-interface-clockA  gpt1_ickti,omap3-interface-clockA  per_96m_fckfixed-factor-clock:Eper_48m_fckfixed-factor-clock!:EBBuart3_fckti,wait-gate-clockB gpt2_gate_fckti,composite-gate-clock CCgpt2_mux_fckti,composite-mux-clock1@DDgpt2_fckti,composite-clockCDgpt3_gate_fckti,composite-gate-clock EEgpt3_mux_fckti,composite-mux-clock1 @FFgpt3_fckti,composite-clockEFgpt4_gate_fckti,composite-gate-clock GGgpt4_mux_fckti,composite-mux-clock1 @HHgpt4_fckti,composite-clockGHgpt5_gate_fckti,composite-gate-clock IIgpt5_mux_fckti,composite-mux-clock1 @JJgpt5_fckti,composite-clockIJgpt6_gate_fckti,composite-gate-clock KKgpt6_mux_fckti,composite-mux-clock1 @LLgpt6_fckti,composite-clockKLgpt7_gate_fckti,composite-gate-clock MMgpt7_mux_fckti,composite-mux-clock1 @NNgpt7_fckti,composite-clockMNgpt8_gate_fckti,composite-gate-clock OOgpt8_mux_fckti,composite-mux-clock1 @PPgpt8_fckti,composite-clockOPgpt9_gate_fckti,composite-gate-clock QQgpt9_mux_fckti,composite-mux-clock1 @RRgpt9_fckti,composite-clockQRper_32k_alwon_fckfixed-factor-clock1:ESSgpio6_dbckti,gate-clockS gpio5_dbckti,gate-clockS gpio4_dbckti,gate-clockS gpio3_dbckti,gate-clockS gpio2_dbckti,gate-clockS wdt3_fckti,wait-gate-clockS per_l4_ickfixed-factor-clock0:ETTgpio6_ickti,omap3-interface-clockT gpio5_ickti,omap3-interface-clockT gpio4_ickti,omap3-interface-clockT gpio3_ickti,omap3-interface-clockT gpio2_ickti,omap3-interface-clockT wdt3_ickti,omap3-interface-clockT uart3_ickti,omap3-interface-clockT uart4_ickti,omap3-interface-clockT gpt9_ickti,omap3-interface-clockT gpt8_ickti,omap3-interface-clockT gpt7_ickti,omap3-interface-clockT gpt6_ickti,omap3-interface-clockT gpt5_ickti,omap3-interface-clockT gpt4_ickti,omap3-interface-clockT gpt3_ickti,omap3-interface-clockT gpt2_ickti,omap3-interface-clockT mcbsp2_ickti,omap3-interface-clockT mcbsp3_ickti,omap3-interface-clockT mcbsp4_ickti,omap3-interface-clockT mcbsp2_gate_fckti,composite-gate-clock8 mcbsp3_gate_fckti,composite-gate-clock8 mcbsp4_gate_fckti,composite-gate-clock8 emu_src_mux_ck ti,mux-clockUVW@XXemu_src_ckti,clkdm-gate-clockXYYpclk_fckti,divider-clockY @#pclkx2_fckti,divider-clockY @#atclk_fckti,divider-clockY @#traceclk_src_fck ti,mux-clockUVW @ZZtraceclk_fckti,divider-clockZ @#secure_32k_fck fixed-clock[[gpt12_fckfixed-factor-clock[:Ewdt1_fckfixed-factor-clock[:Esecurity_l4_ick2fixed-factor-clock0:E\\aes1_ickti,omap3-interface-clock\  rng_ickti,omap3-interface-clock\  sha11_ickti,omap3-interface-clock\  des1_ickti,omap3-interface-clock\  cam_mclkti,gate-clock] cam_ick!ti,omap3-no-wait-interface-clock0 csi2_96m_fckti,gate-clock7 security_l3_ickfixed-factor-clock/:E^^pka_ickti,omap3-interface-clock^  icr_ickti,omap3-interface-clock=  des2_ickti,omap3-interface-clock=  mspro_ickti,omap3-interface-clock=  mailboxes_ickti,omap3-interface-clock=  ssi_l4_ickfixed-factor-clock0:Eeesr1_fckti,wait-gate-clock  sr2_fckti,wait-gate-clock  sr_l4_ickfixed-factor-clock0:Edpll2_fckti,divider-clock @#__dpll2_ckti,omap3-dpll-clock_$@4``dpll2_m2_ckti,divider-clock`D#aaiva2_ckti,wait-gate-clocka modem_fckti,omap3-interface-clock  sad2d_ickti,omap3-interface-clock/  mad2d_ickti,omap3-interface-clock/  mspro_fckti,wait-gate-clock7  ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock  bbssi_ssr_div_fck_3430es2ti,composite-divider-clock  @$ccssi_ssr_fck_3430es2ti,composite-clockbcddssi_sst_fck_3430es2fixed-factor-clockd:Ehsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock<  ~~ssi_ick_3430es2ti,omap3-ssi-interface-clocke  usim_gate_fckti,composite-gate-clock6  ppsys_d2_ckfixed-factor-clock:Eggomap_96m_d2_fckfixed-factor-clock6:Ehhomap_96m_d4_fckfixed-factor-clock6:Eiiomap_96m_d8_fckfixed-factor-clock6:Ejjomap_96m_d10_fckfixed-factor-clock6:E kkdpll5_m2_d4_ckfixed-factor-clockf:Elldpll5_m2_d8_ckfixed-factor-clockf:Emmdpll5_m2_d16_ckfixed-factor-clockf:Enndpll5_m2_d20_ckfixed-factor-clockf:Eoousim_mux_fckti,composite-mux-clock(ghijklmno  @#qqusim_fckti,composite-clockpqusim_ickti,omap3-interface-clockA  dpll5_ckti,omap3-dpll-clock  $ L 4rrdpll5_m2_ckti,divider-clockr P#ffsgx_gate_fckti,composite-gate-clock  zzcore_d3_ckfixed-factor-clock:Esscore_d4_ckfixed-factor-clock:Ettcore_d6_ckfixed-factor-clock:Euuomap_192m_alwon_fckfixed-factor-clock:Evvcore_d2_ckfixed-factor-clock:Ewwsgx_mux_fckti,composite-mux-clock stuvwxy @{{sgx_fckti,composite-clockz{sgx_ickti,wait-gate-clock/  cpefuse_fckti,gate-clock  ts_fckti,gate-clock1  usbtll_fckti,wait-gate-clockf  usbtll_ickti,omap3-interface-clock=  mmchs3_ickti,omap3-interface-clock=  mmchs3_fckti,wait-gate-clock7  dss1_alwon_fck_3430es2ti,dss-gate-clock| dss_ick_3430es2ti,omap3-dss-interface-clock0 usbhost_120m_fckti,gate-clockf usbhost_48m_fckti,dss-gate-clock! usbhost_ickti,omap3-dss-interface-clock0 clockdomainscore_l3_clkdmti,clockdomain}~dpll3_clkdmti,clockdomain dpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainYdpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomain`d2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainrsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain scrm@48002000ti,omap3-scrmH clocksmcbsp5_mux_fckti,composite-mux-clock78 mcbsp5_fckti,composite-clockmcbsp1_mux_fckti,composite-mux-clock78 tmcbsp1_fckti,composite-clockmcbsp2_mux_fckti,composite-mux-clock8 tmcbsp2_fckti,composite-clockmcbsp3_mux_fckti,composite-mux-clock8mcbsp3_fckti,composite-clockmcbsp4_mux_fckti,composite-mux-clock8 mcbsp4_fckti,composite-clockclockdomainscounter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap2-intc `H dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH` ! /`pinmux@48002030 ti,omap3-padconfpinctrl-singleH 08=[xdefaultpinmux_hsusb2_pins0      pinmux_uart3_pinsnAppinmux_tfp410_pinspinmux_dss_dpi_pinspinmux_twl4030_pinsApinmux@48002a00 ti,omap3-padconfpinctrl-singleH*\=[pinmux_gpio1_pinsApinmux_twl4030_vpins tisyscon@48002270sysconH"ppbias_regulatorti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-gpio@48310000ti,omap3-gpioH1gpio1 xdefaultgpio@49050000ti,omap3-gpioIgpio2 gpio@49052000ti,omap3-gpioI gpio3 gpio@49054000ti,omap3-gpioI@ gpio4 gpio@49056000ti,omap3-gpioI`!gpio5 gpio@49058000ti,omap3-gpioI"gpio6 serial@4806a000ti,omap3-uartH H,121txrxuart1lserial@4806c000ti,omap3-uartHI,341txrxuart2lserial@49020000ti,omap3-uartIJ,561txrxuart3lxdefaulti2c@48070000 ti,omap3-i2cH8,1txrxi2c1'@twl@48H& ti,twl4030xdefaultaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci ;watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 vdd_ehciw@w@Iregulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@Iregulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio ]ittwl4030-usbti,twl4030-usb pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cH 9,1txrxi2c2i2c@48060000 ti,omap3-i2cH=,1txrxi2c3mailbox@48094000ti,omap3-mailboxmailboxH @spi@48098000ti,omap2-mcspiH Amcspi1@,#$%&'()* 1tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH Bmcspi2 ,+,-.1tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [mcspi3 ,1tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi4,FG1tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1 ,=>1txrx'3Cmmc@480b4000ti,omap3-hsmmcH @Vmmc2,/01txrx Mdisabledmmc@480ad000ti,omap3-hsmmcH ^mmc3,MN1txrx Mdisabledmmu@480bd400ti,omap2-iommuH mmu_ispTmmu@5d000000ti,omap2-iommu]mmu_iva Mdisabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@dmpu ;< ncommontxrx~mcbsp1, 1txrx Mdisabledmcbsp@49022000ti,omap3-mcbspI I dmpusidetone>?ncommontxrxsidetone~mcbsp2mcbsp2_sidetone,!"1txrxMokaymcbsp@49024000ti,omap3-mcbspI@I dmpusidetoneYZncommontxrxsidetone~mcbsp3mcbsp3_sidetone,1txrx Mdisabledmcbsp@49026000ti,omap3-mcbspI`dmpu 67 ncommontxrx~mcbsp4,1txrx Mdisabledmcbsp@48096000ti,omap3-mcbspH `dmpu QR ncommontxrx~mcbsp5,1txrx Mdisabledsham@480c3000ti,omap3-shamshamH 0d1smartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs ehci-phyohci@48064400ti,ohci-omap3HD&Lehci@48064800 ti,ehci-omapHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcnusb_otg_hs@480ab000ti,omap3-musbH \]nmcdma usb_otg_hs  'usb2-phy12dss@48050000 ti,omap3-dssHMok dss_corefckxdefaultdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H dprotophypll Mdisabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH Mdisabled dss_rfbifckickencoder@48050c00ti,omap3-vencH Mok dss_vencfck7portendpointCSportendpointC_ssi-controller@48058000 ti,omap3-ssissiMokHHdsysgddGngdd_mpu d ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHdtxrx&CDssi-port@4805b000ti,omap3-ssi-portHHdtxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$=[xdefaultpinmux_hsusb2_2_pins0   " leds gpio-ledspmu_statjbeagleboard::pmu_stat pheartbeatjbeagleboard::usr0 p vheartbeatmmcjbeagleboard::usr1 pvmmc0hsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z phsusb2_phyusb-nop-xceiv soundti,omap-twl4030 omap3beaglegpio_keys gpio-keysuserjuser pencoder@0 ti,tfp410  xdefaultportsport@0endpoint@0Cport@1endpoint@0Cconnector@0dvi-connectorjdviportendpointCconnector@1svideo-connectorjtvportendpointC #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0display1device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cellsti,intc-size#dma-cells#dma-channels#dma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namesbci3v1-supplyregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthstatusti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdda-supplyremote-endpointti,channelsdata-lineslabelgpioslinux,default-triggergpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspti,codeclinux,codegpio-key,wakeuppowerdown-gpiosdigitalddc-i2c-bus