?8(g'var,omap4-var_somti,omap4430ti,omap4&7Variscite OMAP4 SOMchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@48350000Q/ocp/serial@4806a000Y/ocp/serial@4806c000a/ocp/serial@48020000i/ocp/serial@4806e000memoryqmemory}@cpuscpu@0arm,cortex-a9qcpu}  'O 5acpu@1arm,cortex-a9qcpu}interrupt-controller@48241000arm,cortex-a9-gic}H$H$l2-cache-controller@48242000arm,pl310-cache}H$ &local-timer@48240600arm,cortex-a9-twd-timer}H$  2 socti,omap-inframpu ti,omap4-mpu=mpudsp ti,omap3-c64=dspiva ti,ivahd=ivaocpti,omap4-l3-nocsimple-busG=l3_main_1l3_main_2l3_main_3}DD E2  cm1@4a004000 ti,omap4-cm1}J@ clocksextalt_clkin_ckN fixed-clock[DFFpad_clks_src_ckN fixed-clock[pad_clks_ckNti,gate-clockkr}##pad_slimbus_core_clks_ckN fixed-clock[RRsecure_32k_clk_src_ckN fixed-clock[slimbus_src_clkN fixed-clock[slimbus_clkNti,gate-clockkr }$$sys_32k_ckN fixed-clock[))virt_12000000_ckN fixed-clock[**virt_13000000_ckN fixed-clock[]@++virt_16800000_ckN fixed-clock[Y,,virt_19200000_ckN fixed-clock[$--virt_26000000_ckN fixed-clock[..virt_27000000_ckN fixed-clock[//virt_38400000_ckN fixed-clock[I00tie_low_clock_ckN fixed-clock[55utmi_phy_clkout_ckN fixed-clock[YYxclk60mhsp1_ckN fixed-clock[UUxclk60mhsp2_ckN fixed-clock[WWxclk60motg_ckN fixed-clock[ZZdpll_abe_ckNti,omap4-dpll-m4xen-clockk}dpll_abe_x2_ckNti,omap4-dpll-x2-clockk}dpll_abe_m2x2_ckNti,divider-clockk}  abe_24m_fclkNfixed-factor-clockk abe_clkNti,divider-clockk }  aess_fclkNti,divider-clockk r}(dpll_abe_m3x2_ckNti,divider-clockk}  core_hsd_byp_clk_mux_ckN ti,mux-clockk r},  dpll_core_ckNti,omap4-dpll-core-clockk } $,(dpll_core_x2_ckNti,omap4-dpll-x2-clockkdpll_core_m6x2_ckNti,divider-clockk}@44dpll_core_m2_ckNti,divider-clockk}0ddrphy_ckNfixed-factor-clockkdpll_core_m5x2_ckNti,divider-clockk}<div_core_ckNti,divider-clockk}div_iva_hs_clkNti,divider-clockk}div_mpu_hs_clkNti,divider-clockk}dpll_core_m4x2_ckNti,divider-clockk}8dll_clk_div_ckNfixed-factor-clockkdpll_abe_m2_ckNti,divider-clockk}dpll_core_m3x2_gate_ckN ti,composite-no-wait-gate-clockkr}4dpll_core_m3x2_div_ckNti,composite-divider-clockk}4dpll_core_m3x2_ckNti,composite-clockk^^dpll_core_m7x2_ckNti,divider-clockk}DIIiva_hsd_byp_clk_mux_ckN ti,mux-clockk r}dpll_iva_ckNti,omap4-dpll-clockk }dpll_iva_x2_ckNti,omap4-dpll-x2-clockkdpll_iva_m4x2_ckNti,divider-clockk}dpll_iva_m5x2_ckNti,divider-clockk}dpll_mpu_ckNti,omap4-dpll-clockk }`dlhdpll_mpu_m2_ckNti,divider-clockk}pper_hs_clk_div_ckNfixed-factor-clockk ::usb_hs_clk_div_ckNfixed-factor-clockk @@l3_div_ckNti,divider-clockkr}l4_div_ckNti,divider-clockkr}\\lp_clk_div_ckNfixed-factor-clockk 11mpu_periphclkNfixed-factor-clockkocp_abe_iclkNti,divider-clockkr}(per_abe_24m_fclkNfixed-factor-clockkPPdmic_sync_mux_ckN ti,mux-clock k !r}8""func_dmic_abe_gfclkN ti,mux-clock k"#$r}8mcasp_sync_mux_ckN ti,mux-clock k !r}@%%func_mcasp_abe_gfclkN ti,mux-clock k%#$r}@mcbsp1_sync_mux_ckN ti,mux-clock k !r}H&&func_mcbsp1_gfclkN ti,mux-clock k&#$r}Hmcbsp2_sync_mux_ckN ti,mux-clock k !r}P''func_mcbsp2_gfclkN ti,mux-clock k'#$r}Pmcbsp3_sync_mux_ckN ti,mux-clock k !r}X((func_mcbsp3_gfclkN ti,mux-clock k(#$r}Xslimbus1_fclk_1Nti,gate-clockk!r }`slimbus1_fclk_0Nti,gate-clockkr}`slimbus1_fclk_2Nti,gate-clockk#r }`slimbus1_slimbus_clkNti,gate-clockk$r }`timer5_sync_muxN ti,mux-clockk )r}htimer6_sync_muxN ti,mux-clockk )r}ptimer7_sync_muxN ti,mux-clockk )r}xtimer8_sync_muxN ti,mux-clockk )r}dummy_ckN fixed-clock[clockdomainsprm@4a306000 ti,omap4-prm}J0`0clockssys_clkin_ckN ti,mux-clockk*+,-./0}  abe_dpll_bypass_clk_mux_ckN ti,mux-clockk )r}abe_dpll_refclk_mux_ckN ti,mux-clockk )} dbgclk_mux_ckNfixed-factor-clockk l4_wkup_clk_mux_ckN ti,mux-clockk 1}SSsyc_clk_div_ckNti,divider-clockk }  gpio1_dbclkNti,gate-clockk)r}8dmt1_clk_muxN ti,mux-clockk )r}@usim_ckNti,divider-clockk2r}X33usim_fclkNti,gate-clockk3r}Xpmd_stm_clock_mux_ckN ti,mux-clock k 45r} 66pmd_trace_clk_mux_ckN ti,mux-clock k 45r} 77stm_clk_div_ckNti,divider-clockk6r@} trace_clk_div_div_ckNti,divider-clockk7r} 88trace_clk_div_ckNti,clkdm-gate-clockk899bandgap_fclkNti,gate-clockk)r}clockdomainsemu_sys_clkdmti,clockdomaink9cm2@4a008000 ti,omap4-cm2}J0clocksper_hsd_byp_clk_mux_ckN ti,mux-clockk :r}L;;dpll_per_ckNti,omap4-dpll-clockk ;}@DLH<<dpll_per_m2_ckNti,divider-clockk<}PDDdpll_per_x2_ckNti,omap4-dpll-x2-clockk<}P==dpll_per_m2x2_ckNti,divider-clockk=}PCCdpll_per_m3x2_gate_ckN ti,composite-no-wait-gate-clockk=r}T>>dpll_per_m3x2_div_ckNti,composite-divider-clockk=}T??dpll_per_m3x2_ckNti,composite-clockk>?__dpll_per_m4x2_ckNti,divider-clockk=}X22dpll_per_m5x2_ckNti,divider-clockk=}\GGdpll_per_m6x2_ckNti,divider-clockk=}`BBdpll_per_m7x2_ckNti,divider-clockk=}dJJdpll_usb_ckNti,omap4-dpll-j-type-clockk @}AAdpll_usb_clkdcoldo_ckNti,fixed-factor-clockkA}dpll_usb_m2_ckNti,divider-clockkA}EEducati_clk_mux_ckN ti,mux-clockkB}func_12m_fclkNfixed-factor-clockkCfunc_24m_clkNfixed-factor-clockkD!!func_24mc_fclkNfixed-factor-clockkCQQfunc_48m_fclkNti,divider-clockkC}OOfunc_48mc_fclkNfixed-factor-clockkCHHfunc_64m_fclkNti,divider-clockk2}NNfunc_96m_fclkNti,divider-clockkC}KKinit_60m_fclkNti,divider-clockkE}TTper_abe_nc_fclkNti,divider-clockk}LLaes1_fckNti,gate-clockkr}aes2_fckNti,gate-clockkr}dss_sys_clkNti,gate-clockk r } dss_tv_clkNti,gate-clockkFr } dss_dss_clkNti,gate-clockkGr} dss_48mhz_clkNti,gate-clockkHr } dss_fckNti,gate-clockkr} fdif_fckNti,divider-clockk2r}(gpio2_dbclkNti,gate-clockk)r}`gpio3_dbclkNti,gate-clockk)r}hgpio4_dbclkNti,gate-clockk)r}pgpio5_dbclkNti,gate-clockk)r}xgpio6_dbclkNti,gate-clockk)r}sgx_clk_muxN ti,mux-clockkIJr} hsi_fckNti,divider-clockkCr}8iss_ctrlclkNti,gate-clockkKr} mcbsp4_sync_mux_ckN ti,mux-clockkKLr}MMper_mcbsp4_gfclkN ti,mux-clockkM#r}hsmmc1_fclkN ti,mux-clockkNKr}(hsmmc2_fclkN ti,mux-clockkNKr}0ocp2scp_usb_phy_phy_48mNti,gate-clockkOr}sha2md5_fckNti,gate-clockkr}slimbus2_fclk_1Nti,gate-clockkPr }8slimbus2_fclk_0Nti,gate-clockkQr}8slimbus2_slimbus_clkNti,gate-clockkRr }8smartreflex_core_fckNti,gate-clockkSr}8smartreflex_iva_fckNti,gate-clockkSr}0smartreflex_mpu_fckNti,gate-clockkSr}(cm2_dm10_muxN ti,mux-clockk )r}(cm2_dm11_muxN ti,mux-clockk )r}0cm2_dm2_muxN ti,mux-clockk )r}8cm2_dm3_muxN ti,mux-clockk )r}@cm2_dm4_muxN ti,mux-clockk )r}Hcm2_dm9_muxN ti,mux-clockk )r}Pusb_host_fs_fckNti,gate-clockkHr}]]utmi_p1_gfclkN ti,mux-clockkTUr}XVVusb_host_hs_utmi_p1_clkNti,gate-clockkVr}Xutmi_p2_gfclkN ti,mux-clockkTWr}XXXusb_host_hs_utmi_p2_clkNti,gate-clockkXr }Xusb_host_hs_utmi_p3_clkNti,gate-clockkTr }Xusb_host_hs_hsic480m_p1_clkNti,gate-clockkEr }Xusb_host_hs_hsic60m_p1_clkNti,gate-clockkTr }Xusb_host_hs_hsic60m_p2_clkNti,gate-clockkTr }Xusb_host_hs_hsic480m_p2_clkNti,gate-clockkEr}Xusb_host_hs_func48mclkNti,gate-clockkHr}Xusb_host_hs_fckNti,gate-clockkTr}Xotg_60m_gfclkN ti,mux-clockkYZr}`[[usb_otg_hs_xclkNti,gate-clockk[r}`usb_otg_hs_ickNti,gate-clockkr}`usb_phy_cm_clk32kNti,gate-clockk)r}@usb_tll_hs_usb_ch2_clkNti,gate-clockkTr }husb_tll_hs_usb_ch0_clkNti,gate-clockkTr}husb_tll_hs_usb_ch1_clkNti,gate-clockkTr }husb_tll_hs_ickNti,gate-clockk\r}hclockdomainsl3_init_clkdmti,clockdomainkA]scrm@4a30a000ti,omap4-scrm}J0 clocksauxclk0_src_gate_ckN ti,composite-no-wait-gate-clockk^r}``auxclk0_src_mux_ckNti,composite-mux-clock k ^_r}aaauxclk0_src_ckNti,composite-clockk`abbauxclk0_ckNti,divider-clockkbr}rrauxclk1_src_gate_ckN ti,composite-no-wait-gate-clockk^r}ccauxclk1_src_mux_ckNti,composite-mux-clock k ^_r}ddauxclk1_src_ckNti,composite-clockkcdeeauxclk1_ckNti,divider-clockker}ssauxclk2_src_gate_ckN ti,composite-no-wait-gate-clockk^r}ffauxclk2_src_mux_ckNti,composite-mux-clock k ^_r}ggauxclk2_src_ckNti,composite-clockkfghhauxclk2_ckNti,divider-clockkhr}ttauxclk3_src_gate_ckN ti,composite-no-wait-gate-clockk^r}iiauxclk3_src_mux_ckNti,composite-mux-clock k ^_r}jjauxclk3_src_ckNti,composite-clockkijkkauxclk3_ckNti,divider-clockkkr}uuauxclk4_src_gate_ckN ti,composite-no-wait-gate-clockk^r} llauxclk4_src_mux_ckNti,composite-mux-clock k ^_r} mmauxclk4_src_ckNti,composite-clockklmnnauxclk4_ckNti,divider-clockknr} vvauxclk5_src_gate_ckN ti,composite-no-wait-gate-clockk^r}$ooauxclk5_src_mux_ckNti,composite-mux-clock k ^_r}$ppauxclk5_src_ckNti,composite-clockkopqqauxclk5_ckNti,divider-clockkqr}$wwauxclkreq0_ckN ti,mux-clockkrstuvwr}auxclkreq1_ckN ti,mux-clockkrstuvwr}auxclkreq2_ckN ti,mux-clockkrstuvwr}auxclkreq3_ckN ti,mux-clockkrstuvwr}auxclkreq4_ckN ti,mux-clockkrstuvwr} auxclkreq5_ckN ti,mux-clockkrstuvwr}$clockdomainscounter@4a304000ti,omap-counter32k}J0@  =counter_32kpinmux@4a100040 ti,omap4-padconfpinctrl-single}J@/Mpinmux@4a31e040 ti,omap4-padconfpinctrl-single}J1@8/Mdma-controller@4a056000ti,omap4430-sdma}J`02  ju xxgpio@4a310000ti,omap4-gpio}J1 2=gpio1gpio@48055000ti,omap4-gpio}HP 2=gpio2gpio@48057000ti,omap4-gpio}Hp 2=gpio3gpio@48059000ti,omap4-gpio}H 2 =gpio4gpio@4805b000ti,omap4-gpio}H 2!=gpio5gpio@4805d000ti,omap4-gpio}H 2"=gpio6yygpmc@50000000ti,omap4430-gpmc}P 2=gpmckfckserial@4806a000ti,omap4-uart}H 2H=uart1[lserial@4806c000ti,omap4-uart}H 2I=uart2[lserial@48020000ti,omap4-uart}H 2J=uart3[lserial@4806e000ti,omap4-uart}H 2F=uart4[lspinlock@4a0f6000ti,omap4-hwspinlock}J` =spinlocki2c@48070000 ti,omap4-i2c}H 28=i2c1[twl@48}H 2& ti,twl6030rtcti,twl4030-rtc2 regulator-vaux1ti,twl6030-vaux1B@-regulator-vaux2ti,twl6030-vaux2O*regulator-vaux3ti,twl6030-vaux3B@-regulator-vmmcti,twl6030-vmmcO-{{regulator-vppti,twl6030-vppw@&%regulator-vusimti,twl6030-vusimO,@ regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxio,regulator-vusbti,twl6030-vusbregulator-v1v8ti,twl6030-v1v8,regulator-v2v1ti,twl6030-v2v1,regulator-clk32kgti,twl6030-clk32kgusb-comparatorti,twl6030-usb2 pwmti,twl6030-pwm@pwmledti,twl6030-pwmled@i2c@48072000 ti,omap4-i2c}H  29=i2c2[i2c@48060000 ti,omap4-i2c}H 2==i2c3[tmp105@49 ti,tmp105}Ii2c@48350000 ti,omap4-i2c}H5 2>=i2c4[spi@48098000ti,omap4-mcspi}H  2A=mcspi1K@Yx#x$x%x&x'x(x)x* ^tx0rx0tx1rx1tx2rx2tx3rx3eth@0ks8851hn6}&y2 zzspi@4809a000ti,omap4-mcspi}H  2B=mcspi2K Yx+x,x-x.^tx0rx0tx1rx1spi@480b8000ti,omap4-mcspi}H  2[=mcspi3KYxx^tx0rx0spi@480ba000ti,omap4-mcspi}H  20=mcspi4KYxFxG^tx0rx0mmc@4809c000ti,omap4-hsmmc}H  2S=mmc1Yx=x>^txrx{mmc@480b4000ti,omap4-hsmmc}H @ 2V=mmc2Yx/x0^txrx disabledmmc@480ad000ti,omap4-hsmmc}H  2^=mmc3YxMxN^txrx disabledmmc@480d1000ti,omap4-hsmmc}H  2`=mmc4Yx9x:^txrx disabledmmc@480d5000ti,omap4-hsmmc}H P 2;=mmc5Yx;x<^txrxwdt@4a314000ti,omap4-wdtti,omap3-wdt}J1@ 2P =wd_timer2mcpdm@40132000ti,omap4-mcpdm}@ I mpudma 2p=mcpdmYxAxB^up_linkdn_linkdmic@4012e000ti,omap4-dmic}@Impudma 2r=dmicYxC^up_linkmcbsp@40122000ti,omap4-mcbsp}@ I mpudma 2common=mcbsp1Yx!x"^txrxmcbsp@40124000ti,omap4-mcbsp}@@I@mpudma 2common=mcbsp2Yxx^txrxmcbsp@40126000ti,omap4-mcbsp}@`I`mpudma 2common=mcbsp3Yxx^txrxmcbsp@48096000ti,omap4-mcbsp}H `mpu 2common=mcbsp4Yxx ^txrxkeypad@4a31c000ti,omap4-keypad}J1 2xmpu=kbdemif@4c000000 ti,emif-4d}L 2n=emif1 #8emif@4d000000 ti,emif-4d}M 2o=emif2 #8ocp2scp@4a0ad000ti,omap-ocp2scp}J G=ocp2scp_usb_phyusb2phy@4a0ad080 ti,omap-usb2}J ЀXK|W}}timer@4a318000ti,omap3430-timer}J1 2%=timer1btimer@48032000ti,omap3430-timer}H  2&=timer2timer@48034000ti,omap4430-timer}H@ 2'=timer3timer@48036000ti,omap4430-timer}H` 2(=timer4timer@40138000ti,omap4430-timer}@I 2)=timer5qtimer@4013a000ti,omap4430-timer}@I 2*=timer6qtimer@4013c000ti,omap4430-timer}@I 2+=timer7qtimer@4013e000ti,omap4430-timer}@I 2,=timer8~qtimer@4803e000ti,omap4430-timer}H 2-=timer9~timer@48086000ti,omap3430-timer}H` 2.=timer10~timer@48088000ti,omap4430-timer}H 2/=timer11~usbhstll@4a062000 ti,usbhs-tll}J  2N =usb_tll_hsusbhshost@4a064000ti,usbhs-host}J@ =usb_host_hsGohci@4a064800ti,ohci-omap3usb-ohci}JH& 2Lehci@4a064c00ti,ehci-omapusb-ehci}JL& 2Mcontrol-phy@4a002300ti,control-phy-usb2}J#power||control-phy@4a00233cti,control-phy-otghs}J#<otghs_control~~usb_otg_hs@4a0ab000ti,omap4-musb}J 2\]mcdma =usb_otg_hs}} usb2-phy K~aes@4b501000 ti,omap4-aes=aes}KP 2UYxoxn^txrxdes@480a5000 ti,omap4-des=des}H P 2RYxuxt^txrxbandgap}J"`J#,ti,omap4430-bandgapthermal-zonescpu_thermaltripscpu_alertxpassivecpu_critH xcriticalcooling-mapsmap0 $fixedregulator@0regulator-fixed3VDD_ETH2Z2ZBUzz #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3device_typeregnext-level-cacheoperating-pointsclock-latencycooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodsranges#clock-cellsclock-frequencyclocksti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-mask#dma-cells#dma-channels#dma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initclock-namesregulator-min-microvoltregulator-max-microvoltregulator-always-on#pwm-cellsti,spi-num-csdmasdma-namesspi-max-frequencyvdd-supplyti,dual-voltti,needs-special-resetvmmc-supplyti,bus-widthti,non-removablestatusreg-namesinterrupt-namesti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertctrl-module#phy-cellsti,timer-alwonti,timer-dspti,timer-pwmusb-phyphysphy-namesmultipointnum-epsram-bits#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceregulator-nameenable-active-highregulator-boot-on