98(\$ti,omap4-pandati,omap4430ti,omap4&7TI OMAP4 PandaBoardchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@48350000Q/ocp/serial@4806a000Y/ocp/serial@4806c000a/ocp/serial@48020000i/ocp/serial@4806e000memoryqmemory}@cpuscpu@0arm,cortex-a9qcpu}W0 `O cpu@1arm,cortex-a9qcpu}interrupt-controller@48241000arm,cortex-a9-gic}H$H$l2-cache-controller@48242000arm,pl310-cache}H$ &local-timer@48240600arm,cortex-a9-twd-timer}H$  2 socti,omap-inframpu ti,omap4-mpu=mpudsp ti,omap3-c64=dspiva ti,ivahd=ivaocpti,omap4-l3-nocsimple-busG=l3_main_1l3_main_2l3_main_3}DD E2  cm1@4a004000 ti,omap4-cm1}J@ clocksextalt_clkin_ckN fixed-clock[DHHpad_clks_src_ckN fixed-clock[pad_clks_ckNti,gate-clockkr}##pad_slimbus_core_clks_ckN fixed-clock[TTsecure_32k_clk_src_ckN fixed-clock[slimbus_src_clkN fixed-clock[slimbus_clkNti,gate-clockkr }$$sys_32k_ckN fixed-clock[))virt_12000000_ckN fixed-clock[**virt_13000000_ckN fixed-clock[]@++virt_16800000_ckN fixed-clock[Y,,virt_19200000_ckN fixed-clock[$--virt_26000000_ckN fixed-clock[..virt_27000000_ckN fixed-clock[//virt_38400000_ckN fixed-clock[I00tie_low_clock_ckN fixed-clock[55utmi_phy_clkout_ckN fixed-clock[ZZxclk60mhsp1_ckN fixed-clock[VVxclk60mhsp2_ckN fixed-clock[XXxclk60motg_ckN fixed-clock[[[dpll_abe_ckNti,omap4-dpll-m4xen-clockk}dpll_abe_x2_ckNti,omap4-dpll-x2-clockk}dpll_abe_m2x2_ckNti,divider-clockk}  abe_24m_fclkNfixed-factor-clockk abe_clkNti,divider-clockk }  aess_fclkNti,divider-clockk r}(dpll_abe_m3x2_ckNti,divider-clockk}  core_hsd_byp_clk_mux_ckN ti,mux-clockk r},  dpll_core_ckNti,omap4-dpll-core-clockk } $,(dpll_core_x2_ckNti,omap4-dpll-x2-clockkdpll_core_m6x2_ckNti,divider-clockk}@44dpll_core_m2_ckNti,divider-clockk}0ddrphy_ckNfixed-factor-clockkdpll_core_m5x2_ckNti,divider-clockk}<div_core_ckNti,divider-clockk}div_iva_hs_clkNti,divider-clockk}div_mpu_hs_clkNti,divider-clockk}dpll_core_m4x2_ckNti,divider-clockk}8dll_clk_div_ckNfixed-factor-clockkdpll_abe_m2_ckNti,divider-clockk}dpll_core_m3x2_gate_ckN ti,composite-no-wait-gate-clockkr}4dpll_core_m3x2_div_ckNti,composite-divider-clockk}4dpll_core_m3x2_ckNti,composite-clockk__dpll_core_m7x2_ckNti,divider-clockk}DKKiva_hsd_byp_clk_mux_ckN ti,mux-clockk r}dpll_iva_ckNti,omap4-dpll-clockk }dpll_iva_x2_ckNti,omap4-dpll-x2-clockkdpll_iva_m4x2_ckNti,divider-clockk}dpll_iva_m5x2_ckNti,divider-clockk}dpll_mpu_ckNti,omap4-dpll-clockk }`dlhdpll_mpu_m2_ckNti,divider-clockk}pper_hs_clk_div_ckNfixed-factor-clockk <<usb_hs_clk_div_ckNfixed-factor-clockk BBl3_div_ckNti,divider-clockkr}l4_div_ckNti,divider-clockkr}]]lp_clk_div_ckNfixed-factor-clockk 11mpu_periphclkNfixed-factor-clockkocp_abe_iclkNti,divider-clockkr}(per_abe_24m_fclkNfixed-factor-clockkRRdmic_sync_mux_ckN ti,mux-clock k !r}8""func_dmic_abe_gfclkN ti,mux-clock k"#$r}8mcasp_sync_mux_ckN ti,mux-clock k !r}@%%func_mcasp_abe_gfclkN ti,mux-clock k%#$r}@mcbsp1_sync_mux_ckN ti,mux-clock k !r}H&&func_mcbsp1_gfclkN ti,mux-clock k&#$r}Hmcbsp2_sync_mux_ckN ti,mux-clock k !r}P''func_mcbsp2_gfclkN ti,mux-clock k'#$r}Pmcbsp3_sync_mux_ckN ti,mux-clock k !r}X((func_mcbsp3_gfclkN ti,mux-clock k(#$r}Xslimbus1_fclk_1Nti,gate-clockk!r }`slimbus1_fclk_0Nti,gate-clockkr}`slimbus1_fclk_2Nti,gate-clockk#r }`slimbus1_slimbus_clkNti,gate-clockk$r }`timer5_sync_muxN ti,mux-clockk )r}htimer6_sync_muxN ti,mux-clockk )r}ptimer7_sync_muxN ti,mux-clockk )r}xtimer8_sync_muxN ti,mux-clockk )r}dummy_ckN fixed-clock[clockdomainsprm@4a306000 ti,omap4-prm}J0`0clockssys_clkin_ckN ti,mux-clockk*+,-./0}  abe_dpll_bypass_clk_mux_ckN ti,mux-clockk )r}abe_dpll_refclk_mux_ckN ti,mux-clockk )} dbgclk_mux_ckNfixed-factor-clockk l4_wkup_clk_mux_ckN ti,mux-clockk 1}99syc_clk_div_ckNti,divider-clockk }  gpio1_dbclkNti,gate-clockk)r}8dmt1_clk_muxN ti,mux-clockk )r}@usim_ckNti,divider-clockk2r}X33usim_fclkNti,gate-clockk3r}Xpmd_stm_clock_mux_ckN ti,mux-clock k 45r} 66pmd_trace_clk_mux_ckN ti,mux-clock k 45r} 77stm_clk_div_ckNti,divider-clockk6r@} trace_clk_div_div_ckNti,divider-clockk7r} 88trace_clk_div_ckNti,clkdm-gate-clockk8;;div_ts_ckNti,divider-clockk9r}  ::bandgap_ts_fclkNti,gate-clockk:r}clockdomainsemu_sys_clkdmti,clockdomaink;cm2@4a008000 ti,omap4-cm2}J0clocksper_hsd_byp_clk_mux_ckN ti,mux-clockk <r}L==dpll_per_ckNti,omap4-dpll-clockk =}@DLH>>dpll_per_m2_ckNti,divider-clockk>}PFFdpll_per_x2_ckNti,omap4-dpll-x2-clockk>}P??dpll_per_m2x2_ckNti,divider-clockk?}PEEdpll_per_m3x2_gate_ckN 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fdif_fckNti,divider-clockk2r}(gpio2_dbclkNti,gate-clockk)r}`gpio3_dbclkNti,gate-clockk)r}hgpio4_dbclkNti,gate-clockk)r}pgpio5_dbclkNti,gate-clockk)r}xgpio6_dbclkNti,gate-clockk)r}sgx_clk_muxN ti,mux-clockkKLr} hsi_fckNti,divider-clockkEr}8iss_ctrlclkNti,gate-clockkMr} mcbsp4_sync_mux_ckN ti,mux-clockkMNr}OOper_mcbsp4_gfclkN ti,mux-clockkO#r}hsmmc1_fclkN ti,mux-clockkPMr}(hsmmc2_fclkN ti,mux-clockkPMr}0ocp2scp_usb_phy_phy_48mNti,gate-clockkQr}sha2md5_fckNti,gate-clockkr}slimbus2_fclk_1Nti,gate-clockkRr }8slimbus2_fclk_0Nti,gate-clockkSr}8slimbus2_slimbus_clkNti,gate-clockkTr }8smartreflex_core_fckNti,gate-clockk9r}8smartreflex_iva_fckNti,gate-clockk9r}0smartreflex_mpu_fckNti,gate-clockk9r}(cm2_dm10_muxN ti,mux-clockk )r}(cm2_dm11_muxN ti,mux-clockk )r}0cm2_dm2_muxN ti,mux-clockk )r}8cm2_dm3_muxN ti,mux-clockk )r}@cm2_dm4_muxN ti,mux-clockk )r}Hcm2_dm9_muxN ti,mux-clockk )r}Pusb_host_fs_fckNti,gate-clockkJr}^^utmi_p1_gfclkN ti,mux-clockkUVr}XWWusb_host_hs_utmi_p1_clkNti,gate-clockkWr}Xutmi_p2_gfclkN ti,mux-clockkUXr}XYYusb_host_hs_utmi_p2_clkNti,gate-clockkYr }Xusb_host_hs_utmi_p3_clkNti,gate-clockkUr }Xusb_host_hs_hsic480m_p1_clkNti,gate-clockkGr }Xusb_host_hs_hsic60m_p1_clkNti,gate-clockkUr }Xusb_host_hs_hsic60m_p2_clkNti,gate-clockkUr }Xusb_host_hs_hsic480m_p2_clkNti,gate-clockkGr}Xusb_host_hs_func48mclkNti,gate-clockkJr}Xusb_host_hs_fckNti,gate-clockkUr}Xotg_60m_gfclkN ti,mux-clockkZ[r}`\\usb_otg_hs_xclkNti,gate-clockk\r}`usb_otg_hs_ickNti,gate-clockkr}`usb_phy_cm_clk32kNti,gate-clockk)r}@usb_tll_hs_usb_ch2_clkNti,gate-clockkUr }husb_tll_hs_usb_ch0_clkNti,gate-clockkUr}husb_tll_hs_usb_ch1_clkNti,gate-clockkUr }husb_tll_hs_ickNti,gate-clockk]r}hclockdomainsl3_init_clkdmti,clockdomainkC^scrm@4a30a000ti,omap4-scrm}J0 clocksauxclk0_src_gate_ckN ti,composite-no-wait-gate-clockk_r}aaauxclk0_src_mux_ckNti,composite-mux-clock k _`r}bbauxclk0_src_ckNti,composite-clockkabccauxclk0_ckNti,divider-clockkcr}ssauxclk1_src_gate_ckN ti,composite-no-wait-gate-clockk_r}ddauxclk1_src_mux_ckNti,composite-mux-clock k _`r}eeauxclk1_src_ckNti,composite-clockkdeffauxclk1_ckNti,divider-clockkfr}ttauxclk2_src_gate_ckN ti,composite-no-wait-gate-clockk_r}ggauxclk2_src_mux_ckNti,composite-mux-clock k _`r}hhauxclk2_src_ckNti,composite-clockkghiiauxclk2_ckNti,divider-clockkir}uuauxclk3_src_gate_ckN ti,composite-no-wait-gate-clockk_r}jjauxclk3_src_mux_ckNti,composite-mux-clock k _`r}kkauxclk3_src_ckNti,composite-clockkjkllauxclk3_ckNti,divider-clockklr}vvauxclk4_src_gate_ckN ti,composite-no-wait-gate-clockk_r} mmauxclk4_src_mux_ckNti,composite-mux-clock k _`r} nnauxclk4_src_ckNti,composite-clockkmnooauxclk4_ckNti,divider-clockkor} wwauxclk5_src_gate_ckN ti,composite-no-wait-gate-clockk_r}$ppauxclk5_src_mux_ckNti,composite-mux-clock k _`r}$qqauxclk5_src_ckNti,composite-clockkpqrrauxclk5_ckNti,divider-clockkrr}$xxauxclkreq0_ckN ti,mux-clockkstuvwxr}auxclkreq1_ckN ti,mux-clockkstuvwxr}auxclkreq2_ckN ti,mux-clockkstuvwxr}auxclkreq3_ckN ti,mux-clockkstuvwxr}auxclkreq4_ckN ti,mux-clockkstuvwxr} auxclkreq5_ckN ti,mux-clockkstuvwxr}$clockdomainscounter@4a304000ti,omap-counter32k}J0@  =counter_32kpinmux@4a100040 ti,omap4-padconfpinctrl-single}J@/Mjdefault xyz{|}~pinmux_twl6040_pins`yypinmux_mcpdm_pins(zzpinmux_mcbsp1_pins {{pinmux_dss_dpi_pins"$&(*,.0246tvxz|~||pinmux_tfp410_pinsD}}pinmux_dss_hdmi_pinsZ\^~~pinmux_tpd12s015_pins"HX pinmux_hsusbb1_pins`           pinmux_i2c1_pinspinmux_i2c2_pinspinmux_i2c3_pinspinmux_i2c4_pinspinmux_wl12xx_gpio &,02pinmux_wl12xx_pins@8:  pinmux_twl6030_pins^Agpio_led_pmxpinmux@4a31e040 ti,omap4-padconfpinctrl-single}J1@8/Mpinmux_leds_wkpinspinmux_twl6030_wkup_pinsdma-controller@4a056000ti,omap4430-sdma}J`02   gpio@4a310000ti,omap4-gpio}J1 2=gpio1gpio@48055000ti,omap4-gpio}HP 2=gpio2gpio@48057000ti,omap4-gpio}Hp 2=gpio3gpio@48059000ti,omap4-gpio}H 2 =gpio4gpio@4805b000ti,omap4-gpio}H 2!=gpio5gpio@4805d000ti,omap4-gpio}H 2"=gpio6gpmc@50000000ti,omap4430-gpmc}P 2 =gpmcserial@4806a000ti,omap4-uart}H 2H=uart1[lserial@4806c000ti,omap4-uart}H 2I=uart2[lserial@48020000ti,omap4-uart}H 2J=uart3[lserial@4806e000ti,omap4-uart}H 2F=uart4[lspinlock@4a0f6000ti,omap4-hwspinlock}J` =spinlocki2c@48070000 ti,omap4-i2c}H 28=i2c1jdefaultx[twl@48}H 2& ti,twl6030jdefaultxrtcti,twl4030-rtc2 regulator-vaux1ti,twl6030-vaux10B@H-regulator-vaux2ti,twl6030-vaux20OH*regulator-vaux3ti,twl6030-vaux30B@H-regulator-vmmcti,twl6030-vmmc0OH-regulator-vppti,twl6030-vpp0w@H&%regulator-vusimti,twl6030-vusim0OH,@ regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxio`regulator-vusbti,twl6030-vusbregulator-v1v8ti,twl6030-v1v8`regulator-v2v1ti,twl6030-v2v1`regulator-clk32kgti,twl6030-clk32kgusb-comparatorti,twl6030-usb2 tpwmti,twl6030-pwmpwmledti,twl6030-pwmledtwl@4b ti,twl6040}K 2w& i2c@48072000 ti,omap4-i2c}H  29=i2c2jdefaultx[i2c@48060000 ti,omap4-i2c}H 2==i2c3jdefaultx[eeprom@50 ti,eeprom}Pi2c@48350000 ti,omap4-i2c}H5 2>=i2c4jdefaultx[spi@48098000ti,omap4-mcspi}H  2A=mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap4-mcspi}H  2B=mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap4-mcspi}H  2[=mcspi3tx0rx0spi@480ba000ti,omap4-mcspi}H  20=mcspi4FGtx0rx0mmc@4809c000ti,omap4-hsmmc}H  2S=mmc1=>txrxmmc@480b4000ti,omap4-hsmmc}H @ 2V=mmc2/0txrx disabledmmc@480ad000ti,omap4-hsmmc}H  2^=mmc3MNtxrx disabledmmc@480d1000ti,omap4-hsmmc}H  2`=mmc49:txrx disabledmmc@480d5000ti,omap4-hsmmc}H P 2;=mmc5;<txrxjdefaultx#1wdt@4a314000ti,omap4-wdtti,omap3-wdt}J1@ 2P =wd_timer2mcpdm@40132000ti,omap4-mcpdm}@ I Dmpudma 2p=mcpdmABup_linkdn_linkdmic@4012e000ti,omap4-dmic}@IDmpudma 2r=dmicCup_link disabledmcbsp@40122000ti,omap4-mcbsp}@ I Dmpudma 2Ncommon^=mcbsp1!"txrxmcbsp@40124000ti,omap4-mcbsp}@@I@Dmpudma 2Ncommon^=mcbsp2txrx disabledmcbsp@40126000ti,omap4-mcbsp}@`I`Dmpudma 2Ncommon^=mcbsp3txrx disabledmcbsp@48096000ti,omap4-mcbsp}H `Dmpu 2Ncommon^=mcbsp4 txrxkeypad@4a31c000ti,omap4-keypad}J1 2xDmpu=kbdemif@4c000000 ti,emif-4d}L 2n=emif1mvemif@4d000000 ti,emif-4d}M 2o=emif2mvocp2scp@4a0ad000ti,omap-ocp2scp}J G=ocp2scp_usb_phyusb2phy@4a0ad080 ti,omap-usb2}J ЀXtimer@4a318000ti,omap3430-timer}J1 2%=timer1timer@48032000ti,omap3430-timer}H  2&=timer2timer@48034000ti,omap4430-timer}H@ 2'=timer3timer@48036000ti,omap4430-timer}H` 2(=timer4timer@40138000ti,omap4430-timer}@I 2)=timer5timer@4013a000ti,omap4430-timer}@I 2*=timer6timer@4013c000ti,omap4430-timer}@I 2+=timer7timer@4013e000ti,omap4430-timer}@I 2,=timer8timer@4803e000ti,omap4430-timer}H 2-=timer9timer@48086000ti,omap3430-timer}H` 2.=timer10timer@48088000ti,omap4430-timer}H 2/=timer11usbhstll@4a062000 ti,usbhs-tll}J  2N =usb_tll_hsusbhshost@4a064000ti,usbhs-host}J@ =usb_host_hsG  ehci-phyohci@4a064800ti,ohci-omap3usb-ohci}JH& 2Lehci@4a064c00ti,ehci-omapusb-ehci}JL& 2Mcontrol-phy@4a002300ti,control-phy-usb2}J#Dpowercontrol-phy@4a00233cti,control-phy-otghs}J#<Dotghs_controlusb_otg_hs@4a0ab000ti,omap4-musb}J 2\]Nmcdma =usb_otg_hs $usb2-phy.9A JY2aes@4b501000 ti,omap4-aes=aes}KP 2Uontxrxdes@480a5000 ti,omap4-des=des}H P 2Ruttxrxbandgap}J"`J#,J#xti,omap4460-bandgap 2~ _epmuarm,cortex-a9-pmu267=debugssthermal-zonescpu_thermal{tripscpu_alertxpassivecpu_critH xcriticalcooling-mapsmap0 lpddr2#Elpida,ECB240ABACNjedec,lpddr2-s4 "/<HUbqlpddr2-timings@0jedec,lpddr2-timings~ׄRFP:'LLL:|P_~@B@pplpddr2-timings@1jedec,lpddr2-timings~ RFP:''LL:|P_~@B@ppleds gpio-ledsjdefaultxheartbeatpandaboard::status1 _  heartbeatmmcpandaboard::status2 _ mmc0soundti,abe-twl6040 !PandaBoardES*I7@KHeadset StereophoneHSOLHeadset StereophoneHSORExt SpkHFLExt SpkHFRLine OutAUXLLine OutAUXRAFMLLine InAFMRLine Inhsusb1_power_regregulator-fixed \hsusb1_vbus02ZH2Z kp`|hsusb1_phyusb-nop-xceiv [$wl12xx_vmmcjdefaultxregulator-fixed\vwl12710w@Hw@  kp #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3device_typeregnext-level-cacheoperating-pointsclock-latencycooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodsranges#clock-cellsclock-frequencyclocksti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pins#dma-cells#dma-channels#dma-requeststi,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initregulator-min-microvoltregulator-max-microvoltregulator-always-onusb-supply#pwm-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,spi-num-csdmasdma-namesti,dual-voltti,needs-special-resetvmmc-supplybus-widthstatusnon-removablecap-power-off-cardreg-namesinterrupt-namesti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handlectrl-module#phy-cellsti,timer-alwonti,timer-dspti,timer-pwmport1-modephysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowergpios#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedlabellinux,default-triggerti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingregulator-namestartup-delay-usregulator-boot-onreset-gpiosvcc-supply