8(Dcompulab,omap3-sbc-t3517compulab,omap3-cm-t3517ti,am3517ti,omap3&!7CompuLab SBC-T3517 with CM-T3517chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@4809e000 l/connector@0 u/connector@1memory~memorycpuscpu@0arm,cortex-a8~cpucpupmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocpti,omap3-l3-smxsimple-bush l3_mainaes@480c5000 ti,omap3-aesaesH PPprm@48306000 ti,omap3-prmH0`@ clocksvirt_16_8m_ck fixed-clockYosc_sys_ck ti,mux-clock @  sys_ckti,divider-clock  psys_clkout1ti,gate-clock  pdpll3_x2_ckfixed-factor-clock ,7dpll3_m2x2_ckfixed-factor-clock ,7  dpll4_x2_ckfixed-factor-clock ,7corex2_fckfixed-factor-clock ,7wkup_l4_ickfixed-factor-clock,7@@corex2_d3_fckfixed-factor-clock,7aacorex2_d5_fckfixed-factor-clock,7bbclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock00virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ckti,omap3-dpll-per-clock D 0  dpll4_m2_ckti,divider-clock  ? Hdpll4_m2x2_mul_ckfixed-factor-clock,7dpll4_m2x2_ckti,gate-clock Aomap_96m_alwon_fckfixed-factor-clock,7dpll3_ckti,omap3-dpll-core-clock @ 0  dpll3_m3_ckti,divider-clock  @dpll3_m3x2_mul_ckfixed-factor-clock,7dpll3_m3x2_ckti,gate-clock  Aemu_core_alwon_ckfixed-factor-clock,7TTsys_altclk fixed-clockmcbsp_clks fixed-clock77dpll3_m2_ckti,divider-clock   @  core_ckfixed-factor-clock ,7dpll1_fckti,divider-clock  @dpll1_ckti,omap3-dpll-clock  $ @ 4dpll1_x2_ckfixed-factor-clock,7dpll1_x2m2_ckti,divider-clock  D,,cm_96m_fckfixed-factor-clock,7omap_96m_fck ti,mux-clock @55dpll4_m3_ckti,divider-clock  @dpll4_m3x2_mul_ckfixed-factor-clock,7dpll4_m3x2_ckti,gate-clock Aomap_54m_fck ti,mux-clock @((cm_96m_d2_fckfixed-factor-clock,7omap_48m_fck ti,mux-clock @  omap_12m_fckfixed-factor-clock ,799dpll4_m4_ckti,divider-clock  @!!dpll4_m4x2_mul_ckti,fixed-factor-clock!Wer""dpll4_m4x2_ckti,gate-clock" Arffdpll4_m5_ckti,divider-clock  ?@##dpll4_m5x2_mul_ckti,fixed-factor-clock#Wer$$dpll4_m5x2_ckti,gate-clock$ Ardpll4_m6_ckti,divider-clock  ?@%%dpll4_m6x2_mul_ckfixed-factor-clock%,7&&dpll4_m6x2_ckti,gate-clock& A''emu_per_alwon_ckfixed-factor-clock',7UUclkout2_src_gate_ck ti,composite-no-wait-gate-clock p))clkout2_src_mux_ckti,composite-mux-clock( p**clkout2_src_ckti,composite-clock)*++sys_clkout2ti,divider-clock+ @ pmpu_ckfixed-factor-clock,,7--arm_fckti,divider-clock- $ emu_mpu_alwon_ckfixed-factor-clock-,7VVl3_ickti,divider-clock  @..l4_ickti,divider-clock.  @//rm_ickti,divider-clock/  @gpt10_gate_fckti,composite-gate-clock  11gpt10_mux_fckti,composite-mux-clock0 @22gpt10_fckti,composite-clock12gpt11_gate_fckti,composite-gate-clock  33gpt11_mux_fckti,composite-mux-clock0 @44gpt11_fckti,composite-clock34core_96m_fckfixed-factor-clock5,766mmchs2_fckti,wait-gate-clock6 mmchs1_fckti,wait-gate-clock6 i2c3_fckti,wait-gate-clock6 i2c2_fckti,wait-gate-clock6 i2c1_fckti,wait-gate-clock6 mcbsp5_gate_fckti,composite-gate-clock7  mcbsp1_gate_fckti,composite-gate-clock7  core_48m_fckfixed-factor-clock ,788mcspi4_fckti,wait-gate-clock8 mcspi3_fckti,wait-gate-clock8 mcspi2_fckti,wait-gate-clock8 mcspi1_fckti,wait-gate-clock8 uart2_fckti,wait-gate-clock8 uart1_fckti,wait-gate-clock8  core_12m_fckfixed-factor-clock9,7::hdq_fckti,wait-gate-clock: core_l3_ickfixed-factor-clock.,7;;sdrc_ickti,wait-gate-clock; gggpmc_fckfixed-factor-clock;,7core_l4_ickfixed-factor-clock/,7<<mmchs2_ickti,omap3-interface-clock< mmchs1_ickti,omap3-interface-clock< hdq_ickti,omap3-interface-clock< mcspi4_ickti,omap3-interface-clock< mcspi3_ickti,omap3-interface-clock< mcspi2_ickti,omap3-interface-clock< mcspi1_ickti,omap3-interface-clock< i2c3_ickti,omap3-interface-clock< i2c2_ickti,omap3-interface-clock< i2c1_ickti,omap3-interface-clock< uart2_ickti,omap3-interface-clock< uart1_ickti,omap3-interface-clock<  gpt11_ickti,omap3-interface-clock<  gpt10_ickti,omap3-interface-clock<  mcbsp5_ickti,omap3-interface-clock<  mcbsp1_ickti,omap3-interface-clock<  omapctrl_ickti,omap3-interface-clock< dss_tv_fckti,gate-clock(dss_96m_fckti,gate-clock5dss2_alwon_fckti,gate-clockdummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock ==gpt1_mux_fckti,composite-mux-clock0 @>>gpt1_fckti,composite-clock=>aes2_ickti,omap3-interface-clock< wkup_32k_fckfixed-factor-clock0,7??gpio1_dbckti,gate-clock? sha12_ickti,omap3-interface-clock< wdt2_fckti,wait-gate-clock? wdt2_ickti,omap3-interface-clock@ wdt1_ickti,omap3-interface-clock@ gpio1_ickti,omap3-interface-clock@ omap_32ksync_ickti,omap3-interface-clock@ gpt12_ickti,omap3-interface-clock@ gpt1_ickti,omap3-interface-clock@ per_96m_fckfixed-factor-clock,7per_48m_fckfixed-factor-clock ,7AAuart3_fckti,wait-gate-clockA nngpt2_gate_fckti,composite-gate-clockBBgpt2_mux_fckti,composite-mux-clock0@CCgpt2_fckti,composite-clockBCgpt3_gate_fckti,composite-gate-clockDDgpt3_mux_fckti,composite-mux-clock0@EEgpt3_fckti,composite-clockDEgpt4_gate_fckti,composite-gate-clockFFgpt4_mux_fckti,composite-mux-clock0@GGgpt4_fckti,composite-clockFGgpt5_gate_fckti,composite-gate-clockHHgpt5_mux_fckti,composite-mux-clock0@IIgpt5_fckti,composite-clockHIgpt6_gate_fckti,composite-gate-clockJJgpt6_mux_fckti,composite-mux-clock0@KKgpt6_fckti,composite-clockJKgpt7_gate_fckti,composite-gate-clockLLgpt7_mux_fckti,composite-mux-clock0@MMgpt7_fckti,composite-clockLMgpt8_gate_fckti,composite-gate-clock NNgpt8_mux_fckti,composite-mux-clock0@OOgpt8_fckti,composite-clockNOgpt9_gate_fckti,composite-gate-clock PPgpt9_mux_fckti,composite-mux-clock0@QQgpt9_fckti,composite-clockPQper_32k_alwon_fckfixed-factor-clock0,7RRgpio6_dbckti,gate-clockRoogpio5_dbckti,gate-clockRppgpio4_dbckti,gate-clockRqqgpio3_dbckti,gate-clockRrrgpio2_dbckti,gate-clockR sswdt3_fckti,wait-gate-clockR ttper_l4_ickfixed-factor-clock/,7SSgpio6_ickti,omap3-interface-clockSuugpio5_ickti,omap3-interface-clockSvvgpio4_ickti,omap3-interface-clockSwwgpio3_ickti,omap3-interface-clockSxxgpio2_ickti,omap3-interface-clockS yywdt3_ickti,omap3-interface-clockS zzuart3_ickti,omap3-interface-clockS {{uart4_ickti,omap3-interface-clockS||gpt9_ickti,omap3-interface-clockS }}gpt8_ickti,omap3-interface-clockS ~~gpt7_ickti,omap3-interface-clockSgpt6_ickti,omap3-interface-clockSgpt5_ickti,omap3-interface-clockSgpt4_ickti,omap3-interface-clockSgpt3_ickti,omap3-interface-clockSgpt2_ickti,omap3-interface-clockSmcbsp2_ickti,omap3-interface-clockSmcbsp3_ickti,omap3-interface-clockSmcbsp4_ickti,omap3-interface-clockSmcbsp2_gate_fckti,composite-gate-clock7mcbsp3_gate_fckti,composite-gate-clock7mcbsp4_gate_fckti,composite-gate-clock7emu_src_mux_ck ti,mux-clockTUV@WWemu_src_ckti,clkdm-gate-clockWXXpclk_fckti,divider-clockX @pclkx2_fckti,divider-clockX @atclk_fckti,divider-clockX @traceclk_src_fck ti,mux-clockTUV@YYtraceclk_fckti,divider-clockY  @secure_32k_fck fixed-clockZZgpt12_fckfixed-factor-clockZ,7wdt1_fckfixed-factor-clockZ,7ipss_ickti,am35xx-interface-clock; hhrmii_ck fixed-clockpclk_ck fixed-clockuart4_ick_am35xxti,omap3-interface-clock< uart4_fck_am35xxti,wait-gate-clock8 dpll5_ckti,omap3-dpll-clock  $ L 4[[dpll5_m2_ckti,divider-clock[  Peesgx_gate_fckti,composite-gate-clock cccore_d3_ckfixed-factor-clock,7\\core_d4_ckfixed-factor-clock,7]]core_d6_ckfixed-factor-clock,7^^omap_192m_alwon_fckfixed-factor-clock,7__core_d2_ckfixed-factor-clock,7``sgx_mux_fckti,composite-mux-clock \]^_`ab @ddsgx_fckti,composite-clockcdsgx_ickti,wait-gate-clock. cpefuse_fckti,gate-clock ts_fckti,gate-clock0 usbtll_fckti,wait-gate-clocke usbtll_ickti,omap3-interface-clock< mmchs3_ickti,omap3-interface-clock< mmchs3_fckti,wait-gate-clock6 dss1_alwon_fck_3430es2ti,dss-gate-clockfrdss_ick_3430es2ti,omap3-dss-interface-clock/usbhost_120m_fckti,gate-clockeusbhost_48m_fckti,dss-gate-clock usbhost_ickti,omap3-dss-interface-clock/clockdomainscore_l3_clkdmti,clockdomainghijklmdpll3_clkdmti,clockdomain dpll1_clkdmti,clockdomainper_clkdmti,clockdomainhnopqrstuvwxyz{|}~emu_clkdmti,clockdomainXdpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomain[sgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain scrm@48002000ti,omap3-scrmH clocksmcbsp5_mux_fckti,composite-mux-clock67mcbsp5_fckti,composite-clockmcbsp1_mux_fckti,composite-mux-clock67tmcbsp1_fckti,composite-clockmcbsp2_mux_fckti,composite-mux-clock7tmcbsp2_fckti,composite-clockmcbsp3_mux_fckti,composite-mux-clock7mcbsp3_fckti,composite-clockmcbsp4_mux_fckti,composite-mux-clock7mcbsp4_fckti,composite-clockemac_ickti,am35xx-gate-clockhiiemac_fckti,gate-clock vpfe_ickti,am35xx-gate-clockhjjvpfe_fckti,gate-clock hsotgusb_ick_am35xxti,am35xx-gate-clockhkkhsotgusb_fck_am35xxti,gate-clockllhecc_ckti,am35xx-gate-clockmmclockdomainscounter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `pinmux@48002030 ti,omap3-padconfpinctrl-singleH 08 =defaultKpinmux_uart3_pinsUnppinmux_mmc1_pins0Upinmux_green_led_pinsUpinmux_dss_dpi_pins_commonUpinmux_dss_dpi_pins_cm_t35x0Upinmux_ads7846_pinsUpinmux_mcspi1_pins Upinmux_i2c1_pinsUpinmux_mcbsp2_pins U pinmux_hsusb1_phy_reset_pinsUHpinmux_hsusb2_phy_reset_pinsUJpinmux_otg_drv_vbusUpinmux_mmc2_pins0U(*,.02pinmux_wl12xx_core_pinsUFpinmux_usb_hub_pinsUTpinmux_smsc2_pinsUpinmux_tfp410_pinsUpinmux_i2c3_pinsUpinmux_sb_t35_audio_ampUpinmux_mmc1_aux_pinsUDpinmux_sb_t35_usb_hub_pinsUpinmux@48002a00 ti,omap3-padconfpinctrl-singleH*\ pinmux_wl12xx_wkup_pinsUtisyscon@48002270sysconH"ppbias_regulatorti,pbias-omapipbias_mmc_omap2430ppbias_mmc_omap2430w@-gpio@48310000ti,omap3-gpioH1gpio1gpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5gpio@49058000ti,omap3-gpioI"gpio6serial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3l=defaultKi2c@48070000 ti,omap3-i2cH8txrxi2c1=defaultKat24@50 at24,24c02Pi2c@48072000 ti,omap3-i2cH 9txrxi2c2i2c@48060000 ti,omap3-i2cH=txrxi2c3=defaultKat24@50 at24,24c02Pmailbox@48094000ti,omap3-mailboxmailboxH @ ' disableddsp 9 Dspi@48098000ti,omap2-mcspiH Amcspi1O@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3=defaultKads7846@0=defaultK ti,ads7846]h`& z spi@4809a000ti,omap2-mcspiH Bmcspi2O +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [mcspi3O tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi4OFGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrx=defaultK", 8 Ammc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx=defaultK,JZ"hmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp{ disabledmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxok=defaultKmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrx disabledsham@480c3000ti,omap3-shamshamH 0d1smartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH  disabledtimer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs ehci-phy ehci-phyohci@48064400ti,ohci-omap3HD&Lehci@48064800 ti,ehci-omapHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcn-ethernet@4,0smsc,lan9221smsc,lan9115=defaultK& &1C]w(-- ):xIcKzK usb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs.9A dss@48050000 ti,omap3-dssHok dss_corefck=defaultKdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH ok dss_vencfckportendpointJZportendpointJfssi-controller@48058000 ti,omap3-ssissi disabledHHsysgddGgdd_mpussi-port@4805a000ti,omap3-ssi-portHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portHHtxrx&EFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hsokay\Gmc=defaultKethernet@0x5c000000ti,am3517-emac davinci_emacokay\CDEFq ethernet@0x5c030000ti,davinci_mdio davinci_mdiookay\B@serial@4809e000ti,omap3-uartuart4 disabledH T76txrxlleds gpio-leds=defaultKledb  cm-t3x:green ; heartbeathsusb1_power_regregulator-fixed phsusb1_vbus2Z2Z)phsusb2_power_regregulator-fixed phsusb2_vbus2Z2Z)phsusb1_phyusb-nop-xceiv]=defaultK :hsusb2_phyusb-nop-xceiv]=defaultK :ads7846-regregulator-fixed pads7846-reg2Z2Zconnector@1svideo-connector tvportendpointJregulator-vmmcregulator-fixedpvmmc2Z2Zwl12xx_vmmc2regulator-fixedpvw1271=defaultKw@w@ )N Fwl12xx_vaux2regulator-fixedpvwl1271_vaux2w@w@encoder@0 ti,tfp410 Y=defaultKportsport@0endpoint@0Jport@1endpoint@0Jconnector@0dvi-connector dviportendpointJaudio_ampregulator-fixed paudio_amp=defaultK i{regulator-vddvario-sb-t35regulator-fixed pvddvario{regulator-vdd33a-sb-t35regulator-fixedpvdd33a{ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3display0display1device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockinterrupt-controller#interrupt-cells#dma-cells#dma-channels#dma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namespagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-replinux,wakeupti,dual-voltpbias-supplybus-widthvmmc-supplywp-gpioscd-gpiosvmmc_aux-supplynon-removablecap-power-off-cardti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-modephysgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsremote-endpointti,channelsdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqlabellinux,default-triggerstartup-delay-usreset-gpiosenable-active-highpowerdown-gpiosenable-active-lowregulator-always-on