Ð þíئ8ÏÄ(âÏŒ$ti,omap4-pandati,omap4430ti,omap4&7TI OMAP4 PandaBoardchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@48350000Q/ocp/serial@4806a000Y/ocp/serial@4806c000a/ocp/serial@48020000i/ocp/serial@4806e000 q/connector@0 z/connector@1memoryƒmemory€@cpuscpu@0arm,cortex-a9ƒcpu“¤«cpu·“à Å“à£è 'ÀO€ 5èa€ûÖèú ££cpu@1arm,cortex-a9ƒcpu“interrupt-controller@48241000arm,cortex-a9-gic,H$H$ l2-cache-controller@48242000arm,pl310-cacheH$ =K local-timer@48240600arm,cortex-a9-twd-timer¤H$  W socti,omap-inframpu ti,omap4-mpubmpuldsp ti,omap3-c64bdspiva ti,ivahdbivaocpti,omap4-l3-nocsimple-busqbl3_main_1l3_main_2l3_main_3DD€ EW  cm1@4a004000 ti,omap4-cm1J@ clocksextalt_clkin_ckx fixed-clock…„DÀ HHpad_clks_src_ckx fixed-clock…· pad_clks_ckxti,gate-clock¤• %%pad_slimbus_core_clks_ckx fixed-clock…· TTsecure_32k_clk_src_ckx fixed-clock…€slimbus_src_clkx fixed-clock…· slimbus_clkxti,gate-clock¤•  &&sys_32k_ckx fixed-clock…€ ++virt_12000000_ckx fixed-clock…· ,,virt_13000000_ckx fixed-clock…Æ]@ --virt_16800000_ckx fixed-clock…Y ..virt_19200000_ckx fixed-clock…$ø //virt_26000000_ckx fixed-clock…Œº€ 00virt_27000000_ckx fixed-clock…›üÀ 11virt_38400000_ckx fixed-clock…Ið 22tie_low_clock_ckx fixed-clock… 77utmi_phy_clkout_ckx fixed-clock…“‡ [[xclk60mhsp1_ckx fixed-clock…“‡ WWxclk60mhsp2_ckx fixed-clock…“‡ YYxclk60motg_ckx fixed-clock…“‡ \\dpll_abe_ckxti,omap4-dpll-m4xen-clock¤ àäìè  dpll_abe_x2_ckxti,omap4-dpll-x2-clock¤ ð  dpll_abe_m2x2_ckxti,divider-clock¤ ¢­ð¿Ö  abe_24m_fclkxfixed-factor-clock¤ íø !!abe_clkxti,divider-clock¤ ¢  aess_fclkxti,divider-clock¤ •¢( dpll_abe_m3x2_ckxti,divider-clock¤ ¢­ô¿Ö core_hsd_byp_clk_mux_ckx ti,mux-clock¤•, dpll_core_ckxti,omap4-dpll-core-clock¤ $,( dpll_core_x2_ckxti,omap4-dpll-x2-clock¤ dpll_core_m6x2_ckxti,divider-clock¤¢­@¿Ö 66dpll_core_m2_ckxti,divider-clock¤¢­0¿Ö ddrphy_ckxfixed-factor-clock¤íødpll_core_m5x2_ckxti,divider-clock¤¢­<¿Ö div_core_ckxti,divider-clock¤¢ div_iva_hs_clkxti,divider-clock¤¢Ü div_mpu_hs_clkxti,divider-clock¤¢œ dpll_core_m4x2_ckxti,divider-clock¤¢­8¿Ö dll_clk_div_ckxfixed-factor-clock¤íødpll_abe_m2_ckxti,divider-clock¤ ¢ð¿  dpll_core_m3x2_gate_ckx ti,composite-no-wait-gate-clock¤•4 dpll_core_m3x2_div_ckxti,composite-divider-clock¤¢4¿ dpll_core_m3x2_ckxti,composite-clock¤ ``dpll_core_m7x2_ckxti,divider-clock¤¢­D¿Ö KKiva_hsd_byp_clk_mux_ckx ti,mux-clock¤•¬ dpll_iva_ckxti,omap4-dpll-clock¤ ¤¬¨ dpll_iva_x2_ckxti,omap4-dpll-x2-clock¤ dpll_iva_m4x2_ckxti,divider-clock¤¢­¸¿Ödpll_iva_m5x2_ckxti,divider-clock¤¢­¼¿Ödpll_mpu_ckxti,omap4-dpll-clock¤`dlh dpll_mpu_m2_ckxti,divider-clock¤¢­p¿Öper_hs_clk_div_ckxfixed-factor-clock¤íø <<usb_hs_clk_div_ckxfixed-factor-clock¤íø BBl3_div_ckxti,divider-clock¤•¢ l4_div_ckxti,divider-clock¤•¢ ^^lp_clk_div_ckxfixed-factor-clock¤ íø 33mpu_periphclkxfixed-factor-clock¤íø ocp_abe_iclkxti,divider-clock¤•(per_abe_24m_fclkxfixed-factor-clock¤ íø RRdmic_sync_mux_ckx ti,mux-clock ¤!"#•8 $$func_dmic_abe_gfclkx ti,mux-clock ¤$%&•8mcasp_sync_mux_ckx ti,mux-clock ¤!"#•@ ''func_mcasp_abe_gfclkx ti,mux-clock ¤'%&•@mcbsp1_sync_mux_ckx ti,mux-clock ¤!"#•H ((func_mcbsp1_gfclkx ti,mux-clock ¤(%&•Hmcbsp2_sync_mux_ckx ti,mux-clock ¤!"#•P ))func_mcbsp2_gfclkx ti,mux-clock ¤)%&•Pmcbsp3_sync_mux_ckx ti,mux-clock ¤!"#•X **func_mcbsp3_gfclkx ti,mux-clock ¤*%&•Xslimbus1_fclk_1xti,gate-clock¤#• `slimbus1_fclk_0xti,gate-clock¤!•`slimbus1_fclk_2xti,gate-clock¤%• `slimbus1_slimbus_clkxti,gate-clock¤&• `timer5_sync_muxx ti,mux-clock¤"+•htimer6_sync_muxx ti,mux-clock¤"+•ptimer7_sync_muxx ti,mux-clock¤"+•xtimer8_sync_muxx ti,mux-clock¤"+•€dummy_ckx fixed-clock…clockdomainsprm@4a306000 ti,omap4-prmJ0`0 W clockssys_clkin_ckx ti,mux-clock¤,-./012¿ abe_dpll_bypass_clk_mux_ckx ti,mux-clock¤+•  abe_dpll_refclk_mux_ckx ti,mux-clock¤+  dbgclk_mux_ckxfixed-factor-clock¤íøl4_wkup_clk_mux_ckx ti,mux-clock¤3 UUsyc_clk_div_ckxti,divider-clock¤¢ ""gpio1_dbclkxti,gate-clock¤+•8dmt1_clk_muxx ti,mux-clock¤+•@usim_ckxti,divider-clock¤4•X 55usim_fclkxti,gate-clock¤5•Xpmd_stm_clock_mux_ckx ti,mux-clock ¤67•  88pmd_trace_clk_mux_ckx ti,mux-clock ¤67•  99stm_clk_div_ckxti,divider-clock¤8•¢@ trace_clk_div_div_ckxti,divider-clock¤9•  ::trace_clk_div_ckxti,clkdm-gate-clock¤: ;;bandgap_fclkxti,gate-clock¤+•ˆclockdomainsemu_sys_clkdmti,clockdomain¤;cm2@4a008000 ti,omap4-cm2J€0clocksper_hsd_byp_clk_mux_ckx ti,mux-clock¤<•L ==dpll_per_ckxti,omap4-dpll-clock¤=@DLH >>dpll_per_m2_ckxti,divider-clock¤>¢P¿ FFdpll_per_x2_ckxti,omap4-dpll-x2-clock¤>P ??dpll_per_m2x2_ckxti,divider-clock¤?¢­P¿Ö EEdpll_per_m3x2_gate_ckx ti,composite-no-wait-gate-clock¤?•T @@dpll_per_m3x2_div_ckxti,composite-divider-clock¤?¢T¿ AAdpll_per_m3x2_ckxti,composite-clock¤@A aadpll_per_m4x2_ckxti,divider-clock¤?¢­X¿Ö 44dpll_per_m5x2_ckxti,divider-clock¤?¢­\¿Ö IIdpll_per_m6x2_ckxti,divider-clock¤?¢­`¿Ö DDdpll_per_m7x2_ckxti,divider-clock¤?¢­d¿Ö LLdpll_usb_ckxti,omap4-dpll-j-type-clock¤B€„Œˆ CCdpll_usb_clkdcoldo_ckxti,fixed-factor-clock¤C$­´1Ödpll_usb_m2_ckxti,divider-clock¤C¢­¿Ö GGducati_clk_mux_ckx ti,mux-clock¤Dfunc_12m_fclkxfixed-factor-clock¤Eíøfunc_24m_clkxfixed-factor-clock¤Fíø ##func_24mc_fclkxfixed-factor-clock¤Eíø SSfunc_48m_fclkxti,divider-clock¤E QQfunc_48mc_fclkxfixed-factor-clock¤Eíø JJfunc_64m_fclkxti,divider-clock¤4 PPfunc_96m_fclkxti,divider-clock¤E MMinit_60m_fclkxti,divider-clock¤G VVper_abe_nc_fclkxti,divider-clock¤ ¢ NNaes1_fckxti,gate-clock¤• aes2_fckxti,gate-clock¤•¨dss_sys_clkxti,gate-clock¤"•   ››dss_tv_clkxti,gate-clock¤H•   ššdss_dss_clkxti,gate-clock¤I• ? ™™dss_48mhz_clkxti,gate-clock¤J•   fdif_fckxti,divider-clock¤4•¢(gpio2_dbclkxti,gate-clock¤+•`gpio3_dbclkxti,gate-clock¤+•hgpio4_dbclkxti,gate-clock¤+•pgpio5_dbclkxti,gate-clock¤+•xgpio6_dbclkxti,gate-clock¤+•€sgx_clk_muxx ti,mux-clock¤KL• hsi_fckxti,divider-clock¤E•¢8iss_ctrlclkxti,gate-clock¤M• mcbsp4_sync_mux_ckx ti,mux-clock¤MN•à OOper_mcbsp4_gfclkx ti,mux-clock¤O%•àhsmmc1_fclkx ti,mux-clock¤PM•(hsmmc2_fclkx ti,mux-clock¤PM•0ocp2scp_usb_phy_phy_48mxti,gate-clock¤Q•àsha2md5_fckxti,gate-clock¤•Èslimbus2_fclk_1xti,gate-clock¤R• 8slimbus2_fclk_0xti,gate-clock¤S•8slimbus2_slimbus_clkxti,gate-clock¤T• 8smartreflex_core_fckxti,gate-clock¤U•8smartreflex_iva_fckxti,gate-clock¤U•0smartreflex_mpu_fckxti,gate-clock¤U•(cm2_dm10_muxx ti,mux-clock¤+•(cm2_dm11_muxx ti,mux-clock¤+•0cm2_dm2_muxx ti,mux-clock¤+•8cm2_dm3_muxx ti,mux-clock¤+•@cm2_dm4_muxx ti,mux-clock¤+•Hcm2_dm9_muxx ti,mux-clock¤+•Pusb_host_fs_fckxti,gate-clock¤J•Ð __utmi_p1_gfclkx ti,mux-clock¤VW•X XXusb_host_hs_utmi_p1_clkxti,gate-clock¤X•Xutmi_p2_gfclkx ti,mux-clock¤VY•X ZZusb_host_hs_utmi_p2_clkxti,gate-clock¤Z• Xusb_host_hs_utmi_p3_clkxti,gate-clock¤V• Xusb_host_hs_hsic480m_p1_clkxti,gate-clock¤G• Xusb_host_hs_hsic60m_p1_clkxti,gate-clock¤V• Xusb_host_hs_hsic60m_p2_clkxti,gate-clock¤V• Xusb_host_hs_hsic480m_p2_clkxti,gate-clock¤G•Xusb_host_hs_func48mclkxti,gate-clock¤J•Xusb_host_hs_fckxti,gate-clock¤V•Xotg_60m_gfclkx ti,mux-clock¤[\•` ]]usb_otg_hs_xclkxti,gate-clock¤]•`usb_otg_hs_ickxti,gate-clock¤•`usb_phy_cm_clk32kxti,gate-clock¤+•@ ••usb_tll_hs_usb_ch2_clkxti,gate-clock¤V• husb_tll_hs_usb_ch0_clkxti,gate-clock¤V•husb_tll_hs_usb_ch1_clkxti,gate-clock¤V• husb_tll_hs_ickxti,gate-clock¤^•hclockdomainsl3_init_clkdmti,clockdomain¤C_scrm@4a30a000ti,omap4-scrmJ0  clocksauxclk0_src_gate_ckx ti,composite-no-wait-gate-clock¤`• bbauxclk0_src_mux_ckxti,composite-mux-clock ¤`a• ccauxclk0_src_ckxti,composite-clock¤bc ddauxclk0_ckxti,divider-clock¤d•¢ ttauxclk1_src_gate_ckx ti,composite-no-wait-gate-clock¤`• eeauxclk1_src_mux_ckxti,composite-mux-clock ¤`a• ffauxclk1_src_ckxti,composite-clock¤ef ggauxclk1_ckxti,divider-clock¤g•¢ uuauxclk2_src_gate_ckx ti,composite-no-wait-gate-clock¤`• hhauxclk2_src_mux_ckxti,composite-mux-clock ¤`a• iiauxclk2_src_ckxti,composite-clock¤hi jjauxclk2_ckxti,divider-clock¤j•¢ vvauxclk3_src_gate_ckx ti,composite-no-wait-gate-clock¤`• kkauxclk3_src_mux_ckxti,composite-mux-clock ¤`a• llauxclk3_src_ckxti,composite-clock¤kl mmauxclk3_ckxti,divider-clock¤m•¢ wwauxclk4_src_gate_ckx ti,composite-no-wait-gate-clock¤`•  nnauxclk4_src_mux_ckxti,composite-mux-clock ¤`a•  ooauxclk4_src_ckxti,composite-clock¤no ppauxclk4_ckxti,divider-clock¤p•¢  xxauxclk5_src_gate_ckx ti,composite-no-wait-gate-clock¤`•$ qqauxclk5_src_mux_ckxti,composite-mux-clock ¤`a•$ rrauxclk5_src_ckxti,composite-clock¤qr ssauxclk5_ckxti,divider-clock¤s•¢$ yyauxclkreq0_ckx ti,mux-clock¤tuvwxy•auxclkreq1_ckx ti,mux-clock¤tuvwxy•auxclkreq2_ckx ti,mux-clock¤tuvwxy•auxclkreq3_ckx ti,mux-clock¤tuvwxy•auxclkreq4_ckx ti,mux-clock¤tuvwxy• auxclkreq5_ckx ti,mux-clock¤tuvwxy•$clockdomainscounter@4a304000ti,omap-counter32kJ0@  bcounter_32kpinmux@4a100040 ti,omap4-padconfpinctrl-singleJ@–,Rpÿdefault›z{|}~ €€pinmux_twl6040_pins¥à` ……pinmux_mcpdm_pins(¥ÆÈÊÌÎ ‘‘pinmux_mcbsp1_pins ¥¾ÀÂÄ ’’pinmux_dss_dpi_pinsà¥"$&(*,.0246tvxz|~€‚„†ˆŠŒŽ’” zzpinmux_tfp410_pins¥D {{pinmux_dss_hdmi_pins¥Z\^ ||pinmux_tpd12s015_pins¥"HX  }}pinmux_hsusbb1_pins`¥‚ „† ˆ Š Œ Ž  ’ ” – ˜  ~~pinmux_i2c1_pins¥âä pinmux_i2c2_pins¥æè ‰‰pinmux_i2c3_pins¥êì ŠŠpinmux_i2c4_pins¥îð ‹‹pinmux_wl12xx_gpio ¥&,02 ªªpinmux_wl12xx_pins@¥8:   pinmux_twl6030_pins¥^A ‚‚pinmux@4a31e040 ti,omap4-padconfpinctrl-singleJ1à@8,Rpÿpinmux_leds_wkpins¥ ¤¤pinmux_twl6030_wkup_pins¥ ƒƒtisyscon@4a1005a0sysconJ p pbias_regulatorti,pbias-omap`¹pbias_mmc_omap4Àpbias_mmc_omap4Ïw@ç-ÆÀ ocmcram@40304000 mmio-sram@0@  dma-controller@4a056000ti,omap4430-sdmaJ`0W  ÿ  ŒŒgpio@4a310000ti,omap4-gpioJ1 Wbgpio1&8H, ¥¥gpio@48055000ti,omap4-gpioHP Wbgpio28H, ¨¨gpio@48057000ti,omap4-gpioHp Wbgpio38H,gpio@48059000ti,omap4-gpioH W bgpio48H, ††gpio@4805b000ti,omap4-gpioH° W!bgpio58H,gpio@4805d000ti,omap4-gpioHÐ W"bgpio68H,gpmc@50000000ti,omap4430-gpmcP WT`bgpmcr¤«fckserial@4806a000ti,omap4-uartH  WHbuart1…Ülserial@4806c000ti,omap4-uartHÀ…I€Übuart2…Ülserial@48020000ti,omap4-uartH…J€buart3…Ülserial@4806e000ti,omap4-uartHà…F€buart4…Ülspinlock@4a0f6000ti,omap4-hwspinlockJ` bspinlock™i2c@48070000 ti,omap4-i2cH W8bi2c1default›…€twl@48H W& ti,twl6030,default›‚ƒrtcti,twl4030-rtcW regulator-vaux1ti,twl6030-vaux1ÏB@ç-ÆÀregulator-vaux2ti,twl6030-vaux2ÏO€ç*¹€regulator-vaux3ti,twl6030-vaux3ÏB@ç-ÆÀregulator-vmmcti,twl6030-vmmcÏO€ç-ÆÀ ŽŽregulator-vppti,twl6030-vppÏw@ç&% regulator-vusimti,twl6030-vusimÏO€ç,@ regulator-vdacti,twl6030-vdac žžregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxio§ œœregulator-vusbti,twl6030-vusb „„regulator-v1v8ti,twl6030-v1v8§ ‡‡regulator-v2v1ti,twl6030-v2v1§ ˆˆusb-comparatorti,twl6030-usbW »„pwmti,twl6030-pwmÆpwmledti,twl6030-pwmledÆtwl@4b ti,twl6040Kdefault›… Ww& цâ‡íˆù §§i2c@48072000 ti,omap4-i2cH  W9bi2c2default›‰…€i2c@48060000 ti,omap4-i2cH W=bi2c3default›Š…†  ­­eeprom@50 ti,eepromPi2c@48350000 ti,omap4-i2cH5 W>bi2c4default›‹…€spi@48098000ti,omap4-mcspiH € WAbmcspi1 @Œ#Œ$Œ%Œ&Œ'Œ(Œ)Œ* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap4-mcspiH   WBbmcspi2  Œ+Œ,Œ-Œ.tx0rx0tx1rx1spi@480b8000ti,omap4-mcspiH € W[bmcspi3 ŒŒtx0rx0spi@480ba000ti,omap4-mcspiH   W0bmcspi4 ŒFŒGtx0rx0mmc@4809c000ti,omap4-hsmmcH À WSbmmc1)6Œ=Œ>txrxMZŽfmmc@480b4000ti,omap4-hsmmcH @ WVbmmc26Œ/Œ0txrx pdisabledmmc@480ad000ti,omap4-hsmmcH Ð W^bmmc36ŒMŒNtxrx pdisabledmmc@480d1000ti,omap4-hsmmcH  W`bmmc46Œ9Œ:txrx pdisabledmmc@480d5000ti,omap4-hsmmcH P W;bmmc56Œ;Œ<txrxdefault›Zwf…mmu@4a066000ti,omap4-iommuJ` Wbmmu_dspmmu@55082000ti,omap4-iommuU  Wdbmmu_ipu˜wdt@4a314000ti,omap4-wdtti,omap3-wdtJ1@€ WP bwd_timer2mcpdm@40132000ti,omap4-mcpdm@ I ®mpudma WpbmcpdmŒAŒBup_linkdn_linkpokaydefault›‘ ¦¦dmic@4012e000ti,omap4-dmic@àIà®mpudma WrbdmicŒCup_link pdisabledmcbsp@40122000ti,omap4-mcbsp@ ÿI ÿ®mpudma W¸commonÈ€bmcbsp1Œ!Œ"txrxpokaydefault›’mcbsp@40124000ti,omap4-mcbsp@@ÿI@ÿ®mpudma W¸commonÈ€bmcbsp2ŒŒtxrx pdisabledmcbsp@40126000ti,omap4-mcbsp@`ÿI`ÿ®mpudma W¸commonÈ€bmcbsp3ŒŒtxrx pdisabledmcbsp@48096000ti,omap4-mcbspH `ÿ®mpu W¸commonÈ€bmcbsp4ŒŒ txrx pdisabledkeypad@4a31c000ti,omap4-keypadJ1À€ Wx®mpubkbddmm@4e000000 ti,omap4-dmmN Wqbdmmemif@4c000000 ti,emif-4dL Wnbemif1r×à÷ (“emif@4d000000 ti,emif-4dM Wobemif2r×à÷ (“ocp2scp@4a0ad000ti,omap-ocp2scpJ Ðqbocp2scp_usb_phyusb2phy@4a0ad080 ti,omap-usb2J ЀX6”¤•«wkupclkB ——mailbox@4a0f4000ti,omap4-mailboxJ@ WbmailboxMYkmbox_ipu } ˆmbox_dsp } ˆtimer@4a318000ti,omap3430-timerJ1€€ W%btimer1“timer@48032000ti,omap3430-timerH € W&btimer2timer@48034000ti,omap4430-timerH@€ W'btimer3timer@48036000ti,omap4430-timerH`€ W(btimer4timer@40138000ti,omap4430-timer@€€I€€ W)btimer5¢timer@4013a000ti,omap4430-timer@ €I € W*btimer6¢timer@4013c000ti,omap4430-timer@À€IÀ€ W+btimer7¢timer@4013e000ti,omap4430-timer@à€Ià€ W,btimer8¯¢timer@4803e000ti,omap4430-timerHà€ W-btimer9¯timer@48086000ti,omap3430-timerH`€ W.btimer10¯timer@48088000ti,omap4430-timerH€€ W/btimer11¯usbhstll@4a062000 ti,usbhs-tllJ  WN busb_tll_hsusbhshost@4a064000ti,usbhs-hostJ@ busb_host_hsq ¤VWY3«refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2 ¼ehci-phyohci@4a064800ti,ohci-omap3JH& WLehci@4a064c00 ti,ehci-omapJL& WMÇ–control-phy@4a002300ti,control-phy-usb2J#®power ””control-phy@4a00233cti,control-phy-otghsJ#<®otghs_control ˜˜usb_otg_hs@4a0ab000ti,omap4-musbJ °ÿW\]¸mcdma busb_otg_hsÌ—Ç— Ôusb2-phyÞéñ 6˜ú 2aes@4b501000 ti,omap4-aesbaesKP  WUŒoŒntxrxdes@480a5000 ti,omap4-desbdesH P  WRŒuŒttxrxregulator-abb-mpu ti,abb-v2Àabb_mpu€¤(29pokayJ0{ÐJ0`®base-addressint-addressxI£èO€èû1Èregulator-abb-iva ti,abb-v2Àabb_iva€¤(29 pdisabledJ0{ØJ0`®base-addressint-addressdss@58000000 ti,omap4-dssX€pok bdss_core¤™«fckqdispc@58001000ti,omap4-dispcX W bdss_dispc¤™«fckencoder@58002000ti,omap4-rfbiX  pdisabled bdss_rfbi¤™«fckickencoder@58003000ti,omap4-vencX0 pdisabled bdss_venc¤š«fckencoder@58004000 ti,omap4-dsiX@XB@XC ®protophypll W5 pdisabled bdss_dsi1¤™› «fcksys_clkencoder@58005000 ti,omap4-dsiXPXR@XS ®protophypll WTpok bdss_dsi2¤™› «fcksys_clkUœencoder@58006000ti,omap4-hdmi X`XbXcXd®wppllphycore Wepok bdss_hdmi¤› «fcksys_clkŒL audio_tx`žportendpointlŸ ¯¯portendpointl | ««bandgapJ"`J#,ti,omap4430-bandgap‡ ¡¡thermal-zonescpu_thermalú³èÁ¡tripscpu_alertц ÝЊpassive ¢¢cpu_critÑèHÝÐ Šcriticalcooling-mapsmap0è¢ í£ÿÿÿÿÿÿÿÿlpddr2#Elpida,ECB240ABACNjedec,lpddr2-s4ü  (4DQ^jw„“ ““lpddr2-timings@0jedec,lpddr2-timings ˜–€©ׄ²R¸FP½:˜Á¤Ê'ÏLÔLØLÝ:˜ä|ïÃPô_ú~@B@pplpddr2-timings@1jedec,lpddr2-timings ˜–€© ë²R¸FP½:˜Á¤Ê'Ï'ÔLØLÝ:˜ä|ïÃPô_ú~@B@ppleds gpio-ledsdefault›¤heartbeat'pandaboard::status1 -¥ 3heartbeatmmc'pandaboard::status2 -¥3mmc0soundti,abe-twl6040 IPandaBoardRIð_¦h§¯sHeadset StereophoneHSOLHeadset StereophoneHSORExt SpkHFLExt SpkHFRLine OutAUXLLine OutAUXRHSMICHeadset MicHeadset MicHeadset Mic BiasAFMLLine InAFMRLine Inhsusb1_power_regregulator-fixed Àhsusb1_vbusÏ2Z ç2Z  Ý¥„pù§• ©©hsusb1_phyusb-nop-xceiv §¨³©¤w «main_clk…$ø ––wl12xx_vmmcdefault›ªregulator-fixedÀvwl1271Ïw@çw@ ݨ „pù encoder@0 ti,tfp410 ¾¥portsport@0endpoint@0l«   port@1endpoint@0l¬ ®®connector@0dvi-connector'dviÎÖ­portendpointl® ¬¬encoder@1 ti,tpd12s015$-¨¨ ¨portsport@0endpoint@0l¯ ŸŸport@1endpoint@0l° ±±connector@1hdmi-connector'hdmiŠaportendpointl± °° #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1device_typeregnext-level-cacheclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cells#dma-channels#dma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extended#hwlock-cellsregulator-always-onusb-supply#pwm-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,spi-num-csdmasdma-namesti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthstatusnon-removablecap-power-off-cardti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handlectrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmport1-modephysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedlabelgpioslinux,default-triggerti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingstartup-delay-usregulator-boot-onreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus