8<(!ti,am3517-evmti,am3517ti,omap3&&7TI AM3517 EVM (AM3517/05 TMDSEVM3517)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@4809e000memorylmemoryxcpuscpu@0arm,cortex-a8lcpux|cpupmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busxh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busx  pinmux@30 ti,omap3-padconfpinctrl-singlex08scm_conf@270sysconxp0!'clocksmcbsp5_mux_fck/ti,composite-mux-clock|<xh!'mcbsp5_fck/ti,composite-clock|mcbsp1_mux_fck/ti,composite-mux-clock|<x!'mcbsp1_fck/ti,composite-clock|mcbsp2_mux_fck/ti,composite-mux-clock| <x! ' mcbsp2_fck/ti,composite-clock| mcbsp3_mux_fck/ti,composite-mux-clock| xh! ' mcbsp3_fck/ti,composite-clock| mcbsp4_mux_fck/ti,composite-mux-clock| <xh!'mcbsp4_fck/ti,composite-clock|emac_ick/ti,am35xx-gate-clock|x<!w'wemac_fck/ti,gate-clock|x< vpfe_ick/ti,am35xx-gate-clock|x<!x'xvpfe_fck/ti,gate-clock|x< hsotgusb_ick_am35xx/ti,am35xx-gate-clock|x<!y'yhsotgusb_fck_am35xx/ti,gate-clock|x<!z'zhecc_ck/ti,am35xx-gate-clock|x<!{'{clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \aes@480c5000 ti,omap3-aesaesxH PPIABNtxrxprm@48306000 ti,omap3-prmxH0`@ clocksvirt_16_8m_ck/ fixed-clockXY!'osc_sys_ck/ ti,mux-clock|x @!'sys_ck/ti,divider-clock|<hxps!'sys_clkout1/ti,gate-clock|x p<dpll3_x2_ck/fixed-factor-clock|dpll3_m2x2_ck/fixed-factor-clock|!'dpll4_x2_ck/fixed-factor-clock|corex2_fck/fixed-factor-clock|! ' wkup_l4_ick/fixed-factor-clock|!O'Ocorex2_d3_fck/fixed-factor-clock| !p'pcorex2_d5_fck/fixed-factor-clock| !q'qclockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclk/ fixed-clockXomap_32k_fck/ fixed-clockX!A'Avirt_12m_ck/ fixed-clockX!'virt_13m_ck/ fixed-clockX]@!'virt_19200000_ck/ fixed-clockX$!'virt_26000000_ck/ fixed-clockX!'virt_38_4m_ck/ fixed-clockXI!'dpll4_ck/ti,omap3-dpll-per-clock|x D 0!'dpll4_m2_ck/ti,divider-clock|h?x Hs!!'!dpll4_m2x2_mul_ck/fixed-factor-clock|!!"'"dpll4_m2x2_ck/ti,gate-clock|"<x !#'#omap_96m_alwon_fck/fixed-factor-clock|#!*'*dpll3_ck/ti,omap3-dpll-core-clock|x @ 0!'dpll3_m3_ck/ti,divider-clock|<hx@s!$'$dpll3_m3x2_mul_ck/fixed-factor-clock|$!%'%dpll3_m3x2_ck/ti,gate-clock|%< x !&'&emu_core_alwon_ck/fixed-factor-clock|&!c'csys_altclk/ fixed-clockX!/'/mcbsp_clks/ fixed-clockX!'dpll3_m2_ck/ti,divider-clock|<hx @s!'core_ck/fixed-factor-clock|!'''dpll1_fck/ti,divider-clock|'<hx @s!('(dpll1_ck/ti,omap3-dpll-clock|(x  $ @ 4!'dpll1_x2_ck/fixed-factor-clock|!)')dpll1_x2m2_ck/ti,divider-clock|)hx Ds!='=cm_96m_fck/fixed-factor-clock|*!+'+omap_96m_fck/ ti,mux-clock|+<x @!F'Fdpll4_m3_ck/ti,divider-clock|<h x@s!,',dpll4_m3x2_mul_ck/fixed-factor-clock|,!-'-dpll4_m3x2_ck/ti,gate-clock|-<x !.'.omap_54m_fck/ ti,mux-clock|./<x @!9'9cm_96m_d2_fck/fixed-factor-clock|+!0'0omap_48m_fck/ ti,mux-clock|0/<x @!1'1omap_12m_fck/fixed-factor-clock|1!H'Hdpll4_m4_ck/ti,divider-clock|h x@s!2'2dpll4_m4x2_mul_ck/ti,fixed-factor-clock|2!3'3dpll4_m4x2_ck/ti,gate-clock|3<x !u'udpll4_m5_ck/ti,divider-clock|h?x@s!4'4dpll4_m5x2_mul_ck/ti,fixed-factor-clock|4!5'5dpll4_m5x2_ck/ti,gate-clock|5<x dpll4_m6_ck/ti,divider-clock|<h?x@s!6'6dpll4_m6x2_mul_ck/fixed-factor-clock|6!7'7dpll4_m6x2_ck/ti,gate-clock|7<x !8'8emu_per_alwon_ck/fixed-factor-clock|8!d'dclkout2_src_gate_ck/ ti,composite-no-wait-gate-clock|'<x p!:':clkout2_src_mux_ck/ti,composite-mux-clock|'+9x p!;';clkout2_src_ck/ti,composite-clock|:;!<'<sys_clkout2/ti,divider-clock|<<h@x pmpu_ck/fixed-factor-clock|=!>'>arm_fck/ti,divider-clock|>x $hemu_mpu_alwon_ck/fixed-factor-clock|>!e'el3_ick/ti,divider-clock|'hx @s!?'?l4_ick/ti,divider-clock|?<hx @s!@'@rm_ick/ti,divider-clock|@<hx @sgpt10_gate_fck/ti,composite-gate-clock|< x !B'Bgpt10_mux_fck/ti,composite-mux-clock|A<x @!C'Cgpt10_fck/ti,composite-clock|BCgpt11_gate_fck/ti,composite-gate-clock|< x !D'Dgpt11_mux_fck/ti,composite-mux-clock|A<x @!E'Egpt11_fck/ti,composite-clock|DEcore_96m_fck/fixed-factor-clock|F!'mmchs2_fck/ti,wait-gate-clock|x <!'mmchs1_fck/ti,wait-gate-clock|x <!'i2c3_fck/ti,wait-gate-clock|x <!'i2c2_fck/ti,wait-gate-clock|x <!'i2c1_fck/ti,wait-gate-clock|x <!'mcbsp5_gate_fck/ti,composite-gate-clock|< x !'mcbsp1_gate_fck/ti,composite-gate-clock|< x !'core_48m_fck/fixed-factor-clock|1!G'Gmcspi4_fck/ti,wait-gate-clock|Gx <!'mcspi3_fck/ti,wait-gate-clock|Gx <!'mcspi2_fck/ti,wait-gate-clock|Gx <!'mcspi1_fck/ti,wait-gate-clock|Gx <!'uart2_fck/ti,wait-gate-clock|Gx <!'uart1_fck/ti,wait-gate-clock|Gx < !'core_12m_fck/fixed-factor-clock|H!I'Ihdq_fck/ti,wait-gate-clock|Ix <!'core_l3_ick/fixed-factor-clock|?!J'Jsdrc_ick/ti,wait-gate-clock|Jx <!v'vgpmc_fck/fixed-factor-clock|Jcore_l4_ick/fixed-factor-clock|@!K'Kmmchs2_ick/ti,omap3-interface-clock|Kx <!'mmchs1_ick/ti,omap3-interface-clock|Kx <!'hdq_ick/ti,omap3-interface-clock|Kx <!'mcspi4_ick/ti,omap3-interface-clock|Kx <!'mcspi3_ick/ti,omap3-interface-clock|Kx <!'mcspi2_ick/ti,omap3-interface-clock|Kx <!'mcspi1_ick/ti,omap3-interface-clock|Kx <!'i2c3_ick/ti,omap3-interface-clock|Kx <!'i2c2_ick/ti,omap3-interface-clock|Kx <!'i2c1_ick/ti,omap3-interface-clock|Kx <!'uart2_ick/ti,omap3-interface-clock|Kx <!'uart1_ick/ti,omap3-interface-clock|Kx < !'gpt11_ick/ti,omap3-interface-clock|Kx < !'gpt10_ick/ti,omap3-interface-clock|Kx < !'mcbsp5_ick/ti,omap3-interface-clock|Kx < !'mcbsp1_ick/ti,omap3-interface-clock|Kx < !'omapctrl_ick/ti,omap3-interface-clock|Kx <!'dss_tv_fck/ti,gate-clock|9x<!'dss_96m_fck/ti,gate-clock|Fx<!'dss2_alwon_fck/ti,gate-clock|x<!'dummy_ck/ fixed-clockXgpt1_gate_fck/ti,composite-gate-clock|<x !L'Lgpt1_mux_fck/ti,composite-mux-clock|Ax @!M'Mgpt1_fck/ti,composite-clock|LMaes2_ick/ti,omap3-interface-clock|K<x !'wkup_32k_fck/fixed-factor-clock|A!N'Ngpio1_dbck/ti,gate-clock|Nx <!'sha12_ick/ti,omap3-interface-clock|Kx <!'wdt2_fck/ti,wait-gate-clock|Nx <!'wdt2_ick/ti,omap3-interface-clock|Ox <!'wdt1_ick/ti,omap3-interface-clock|Ox <!'gpio1_ick/ti,omap3-interface-clock|Ox <!'omap_32ksync_ick/ti,omap3-interface-clock|Ox <!'gpt12_ick/ti,omap3-interface-clock|Ox <!'gpt1_ick/ti,omap3-interface-clock|Ox <!'per_96m_fck/fixed-factor-clock|*! ' per_48m_fck/fixed-factor-clock|1!P'Puart3_fck/ti,wait-gate-clock|Px< !|'|gpt2_gate_fck/ti,composite-gate-clock|<x!Q'Qgpt2_mux_fck/ti,composite-mux-clock|Ax@!R'Rgpt2_fck/ti,composite-clock|QRgpt3_gate_fck/ti,composite-gate-clock|<x!S'Sgpt3_mux_fck/ti,composite-mux-clock|A<x@!T'Tgpt3_fck/ti,composite-clock|STgpt4_gate_fck/ti,composite-gate-clock|<x!U'Ugpt4_mux_fck/ti,composite-mux-clock|A<x@!V'Vgpt4_fck/ti,composite-clock|UVgpt5_gate_fck/ti,composite-gate-clock|<x!W'Wgpt5_mux_fck/ti,composite-mux-clock|A<x@!X'Xgpt5_fck/ti,composite-clock|WXgpt6_gate_fck/ti,composite-gate-clock|<x!Y'Ygpt6_mux_fck/ti,composite-mux-clock|A<x@!Z'Zgpt6_fck/ti,composite-clock|YZgpt7_gate_fck/ti,composite-gate-clock|<x!['[gpt7_mux_fck/ti,composite-mux-clock|A<x@!\'\gpt7_fck/ti,composite-clock|[\gpt8_gate_fck/ti,composite-gate-clock|< x!]']gpt8_mux_fck/ti,composite-mux-clock|A<x@!^'^gpt8_fck/ti,composite-clock|]^gpt9_gate_fck/ti,composite-gate-clock|< x!_'_gpt9_mux_fck/ti,composite-mux-clock|A<x@!`'`gpt9_fck/ti,composite-clock|_`per_32k_alwon_fck/fixed-factor-clock|A!a'agpio6_dbck/ti,gate-clock|ax<!}'}gpio5_dbck/ti,gate-clock|ax<!~'~gpio4_dbck/ti,gate-clock|ax<!'gpio3_dbck/ti,gate-clock|ax<!'gpio2_dbck/ti,gate-clock|ax< !'wdt3_fck/ti,wait-gate-clock|ax< !'per_l4_ick/fixed-factor-clock|@!b'bgpio6_ick/ti,omap3-interface-clock|bx<!'gpio5_ick/ti,omap3-interface-clock|bx<!'gpio4_ick/ti,omap3-interface-clock|bx<!'gpio3_ick/ti,omap3-interface-clock|bx<!'gpio2_ick/ti,omap3-interface-clock|bx< !'wdt3_ick/ti,omap3-interface-clock|bx< !'uart3_ick/ti,omap3-interface-clock|bx< !'uart4_ick/ti,omap3-interface-clock|bx<!'gpt9_ick/ti,omap3-interface-clock|bx< !'gpt8_ick/ti,omap3-interface-clock|bx< !'gpt7_ick/ti,omap3-interface-clock|bx<!'gpt6_ick/ti,omap3-interface-clock|bx<!'gpt5_ick/ti,omap3-interface-clock|bx<!'gpt4_ick/ti,omap3-interface-clock|bx<!'gpt3_ick/ti,omap3-interface-clock|bx<!'gpt2_ick/ti,omap3-interface-clock|bx<!'mcbsp2_ick/ti,omap3-interface-clock|bx<!'mcbsp3_ick/ti,omap3-interface-clock|bx<!'mcbsp4_ick/ti,omap3-interface-clock|bx<!'mcbsp2_gate_fck/ti,composite-gate-clock|<x! ' mcbsp3_gate_fck/ti,composite-gate-clock|<x! ' mcbsp4_gate_fck/ti,composite-gate-clock|<x!'emu_src_mux_ck/ ti,mux-clock|cdex@!f'femu_src_ck/ti,clkdm-gate-clock|f!g'gpclk_fck/ti,divider-clock|g<hx@spclkx2_fck/ti,divider-clock|g<hx@satclk_fck/ti,divider-clock|g<hx@straceclk_src_fck/ ti,mux-clock|cde<x@!h'htraceclk_fck/ti,divider-clock|h< hx@ssecure_32k_fck/ fixed-clockX!i'igpt12_fck/fixed-factor-clock|iwdt1_fck/fixed-factor-clock|iipss_ick/ti,am35xx-interface-clock|Jx <!'rmii_ck/ fixed-clockX!'pclk_ck/ fixed-clockX!'uart4_ick_am35xx/ti,omap3-interface-clock|Kx <uart4_fck_am35xx/ti,wait-gate-clock|Gx <dpll5_ck/ti,omap3-dpll-clock|x  $ L 4 !j'jdpll5_m2_ck/ti,divider-clock|jhx Ps!t'tsgx_gate_fck/ti,composite-gate-clock|'<x !r'rcore_d3_ck/fixed-factor-clock|'!k'kcore_d4_ck/fixed-factor-clock|'!l'lcore_d6_ck/fixed-factor-clock|'!m'momap_192m_alwon_fck/fixed-factor-clock|#!n'ncore_d2_ck/fixed-factor-clock|'!o'osgx_mux_fck/ti,composite-mux-clock |klm+nopqx @!s'ssgx_fck/ti,composite-clock|rssgx_ick/ti,wait-gate-clock|?x <!'cpefuse_fck/ti,gate-clock|x <!'ts_fck/ti,gate-clock|Ax <!'usbtll_fck/ti,wait-gate-clock|tx <!'usbtll_ick/ti,omap3-interface-clock|Kx <!'mmchs3_ick/ti,omap3-interface-clock|Kx <!'mmchs3_fck/ti,wait-gate-clock|x <!'dss1_alwon_fck_3430es2/ti,dss-gate-clock|u<x!'dss_ick_3430es2/ti,omap3-dss-interface-clock|@x<!'usbhost_120m_fck/ti,gate-clock|tx<!'usbhost_48m_fck/ti,dss-gate-clock|1x<!'usbhost_ick/ti,omap3-dss-interface-clock|@x<!'clockdomainscore_l3_clkdmti,clockdomain|vwxyz{dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainh||}~emu_clkdmti,clockdomain|gdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain |dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|dpll5_clkdmti,clockdomain|jsgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH !'dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  +`!'pbias_regulatorti,pbias-omapx8pbias_mmc_omap2430?pbias_mmc_omap2430Nw@f-!'gpio@48310000ti,omap3-gpioxH1gpio1~gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5gpio@49058000ti,omap3-gpioxI"gpio6serial@4806a000ti,omap3-uartxH HI12Ntxrxuart1Xlserial@4806c000ti,omap3-uartxHII34Ntxrxuart2Xlserial@49020000ti,omap3-uartxIJI56Ntxrxuart3Xli2c@48070000 ti,omap3-i2cxH8INtxrxi2c1Xi2c@48072000 ti,omap3-i2cxH 9INtxrxi2c2Xi2c@48060000 ti,omap3-i2cxH=INtxrxi2c3Xmailbox@48094000ti,omap3-mailboxmailboxxH @ disableddsp  spi@48098000ti,omap2-mcspixH Amcspi1@I#$%&'()* Ntx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH Bmcspi2 I+,-.Ntx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [mcspi3 INtx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0mcspi4IFGNtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1I=>Ntxrx!.:mmc@480b4000ti,omap3-hsmmcxH @Vmmc2I/0Ntxrx disabledmmc@480ad000ti,omap3-hsmmcxH ^mmc3IMNNtxrx disabledmmu@480bd400ti,omap2-iommuxH mmu_ispD disabledmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@Tmpu ;< ^commontxrxnmcbsp1I Ntxrx disabledmcbsp@49022000ti,omap3-mcbspxI I Tmpusidetone>?^commontxrxsidetonenmcbsp2mcbsp2_sidetoneI!"Ntxrx disabledmcbsp@49024000ti,omap3-mcbspxI@I TmpusidetoneYZ^commontxrxsidetonenmcbsp3mcbsp3_sidetoneINtxrx disabledmcbsp@49026000ti,omap3-mcbspxI`Tmpu 67 ^commontxrxnmcbsp4INtxrx disabledmcbsp@48096000ti,omap3-mcbspxH `Tmpu QR ^commontxrxnmcbsp5INtxrx disabledsham@480c3000ti,omap3-shamshamxH 0d1IENrxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH  disabledtimer@48318000ti,omap3430-timerxH1%timer1}timer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5timer@4903a000ti,omap3430-timerxI*timer6timer@4903c000ti,omap3430-timerxI+timer7timer@4903e000ti,omap3430-timerxI,timer8timer@49040000ti,omap3430-timerxI-timer9timer@48086000ti,omap3430-timerxH`.timer10timer@48088000ti,omap3430-timerxH/timer11timer@48304000ti,omap3430-timerxH0@_timer12}usbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hsohci@48064400ti,ohci-omap3xHD&Lehci@48064800 ti,ehci-omapxHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcxnusb_otg_hs@480ab000ti,omap3-musbxH \]^mcdma usb_otg_hs dss@48050000 ti,omap3-dssxH disabled dss_core|fckdispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H Tprotophypll disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH  disabled dss_venc|fckssi-controller@48058000 ti,omap3-ssissi disabledxHHTsysgddG^gdd_mpussi-port@4805a000ti,omap3-ssi-portxHHTtxrx&CDssi-port@4805b000ti,omap3-ssi-portxHHTtxrx&EFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hs disabledx\G^mcethernet@0x5c000000ti,am3517-emac davinci_emacokayx\CDEF8 *E ^qethernet@0x5c030000ti,davinci_mdio davinci_mdiookayx\B@serial@4809e000ti,omap3-uartuart4 disabledxH TI76NtxrxXlvmmcregulator-fixed ?vmmc_fixedN2Zf2Z!' #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandle#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extended#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freq