8( ti,omap3-evm-37xxti,omap36xx&7TI OMAP37XX EVM (TMDSEVM3730)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000 l/displaymemoryumemorycpuscpu@0arm,cortex-a8ucpucpus 'O 57pmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-bush l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-bus  pinmux@30 ti,omap3-padconfpinctrl-single08#@Fpinmux_twl4030_pinsNA@Fpinmux_dss_dpi_pins2N@Fpinmux_mmc1_pinsPN "$&@Fpinmux_mmc2_pins0N(*,.A02@Fpinmux_uart3_pinsNnAp@Fpinmux_wl12xx_gpioNPN@Fpinmux_smsc911x_pinsN@Fscm_conf@270sysconp0@Fclocksmcbsp5_mux_fckbti,composite-mux-clockoh@Fmcbsp5_fckbti,composite-clockmcbsp1_mux_fckbti,composite-mux-clocko@ F mcbsp1_fckbti,composite-clock mcbsp2_mux_fckbti,composite-mux-clock o@ F mcbsp2_fckbti,composite-clock mcbsp3_mux_fckbti,composite-mux-clock h@Fmcbsp3_fckbti,composite-clock mcbsp4_mux_fckbti,composite-mux-clock oh@Fmcbsp4_fckbti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \#pinmux_twl4030_vpins N@Fpinmux_dss_dpi_pins10N  @Faes@480c5000 ti,omap3-aesaesH PP|ABtxrxprm@48306000 ti,omap3-prmH0`@ clocksvirt_16_8m_ckb fixed-clockY@Fosc_sys_ckb ti,mux-clock @@Fsys_ckbti,divider-clockop@Fsys_clkout1bti,gate-clock podpll3_x2_ckbfixed-factor-clockdpll3_m2x2_ckbfixed-factor-clock@Fdpll4_x2_ckbfixed-factor-clockcorex2_fckbfixed-factor-clock@Fwkup_l4_ickbfixed-factor-clock@MFMcorex2_d3_fckbfixed-factor-clock@Fcorex2_d5_fckbfixed-factor-clock@Fclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclkb fixed-clockomap_32k_fckb fixed-clock@?F?virt_12m_ckb fixed-clock@Fvirt_13m_ckb fixed-clock]@@Fvirt_19200000_ckb fixed-clock$@Fvirt_26000000_ckb fixed-clock@Fvirt_38_4m_ckb fixed-clockI@Fdpll4_ckbti,omap3-dpll-per-j-type-clock D 0@Fdpll4_m2_ckbti,divider-clock? H@Fdpll4_m2x2_mul_ckbfixed-factor-clock@ F dpll4_m2x2_ckbti,hsdiv-gate-clock o @!F!omap_96m_alwon_fckbfixed-factor-clock!@(F(dpll3_ckbti,omap3-dpll-core-clock @ 0@Fdpll3_m3_ckbti,divider-clocko@@"F"dpll3_m3x2_mul_ckbfixed-factor-clock"@#F#dpll3_m3x2_ckbti,hsdiv-gate-clock#o  @$F$emu_core_alwon_ckbfixed-factor-clock$@aFasys_altclkb fixed-clock@-F-mcbsp_clksb fixed-clock@Fdpll3_m2_ckbti,divider-clocko @@Fcore_ckbfixed-factor-clock@%F%dpll1_fckbti,divider-clock%o @@&F&dpll1_ckbti,omap3-dpll-clock&  $ @ 4@Fdpll1_x2_ckbfixed-factor-clock@'F'dpll1_x2m2_ckbti,divider-clock' D@;F;cm_96m_fckbfixed-factor-clock(@)F)omap_96m_fckb ti,mux-clock)o @@DFDdpll4_m3_ckbti,divider-clocko @@*F*dpll4_m3x2_mul_ckbfixed-factor-clock*@+F+dpll4_m3x2_ckbti,hsdiv-gate-clock+o @,F,omap_54m_fckb ti,mux-clock,-o @@7F7cm_96m_d2_fckbfixed-factor-clock)@.F.omap_48m_fckb ti,mux-clock.-o @@/F/omap_12m_fckbfixed-factor-clock/@FFFdpll4_m4_ckbti,divider-clock @@0F0dpll4_m4x2_mul_ckbti,fixed-factor-clock0@1F1dpll4_m4x2_ckbti,gate-clock1o @Fdpll4_m5_ckbti,divider-clock?@@2F2dpll4_m5x2_mul_ckbti,fixed-factor-clock2@3F3dpll4_m5x2_ckbti,hsdiv-gate-clock3o @iFidpll4_m6_ckbti,divider-clocko?@@4F4dpll4_m6x2_mul_ckbfixed-factor-clock4@5F5dpll4_m6x2_ckbti,hsdiv-gate-clock5o @6F6emu_per_alwon_ckbfixed-factor-clock6@bFbclkout2_src_gate_ckb ti,composite-no-wait-gate-clock%o p@8F8clkout2_src_mux_ckbti,composite-mux-clock%)7 p@9F9clkout2_src_ckbti,composite-clock89@:F:sys_clkout2bti,divider-clock:o@ pmpu_ckbfixed-factor-clock;@<F<arm_fckbti,divider-clock< $emu_mpu_alwon_ckbfixed-factor-clock<@cFcl3_ickbti,divider-clock% @@=F=l4_ickbti,divider-clock=o @@>F>rm_ickbti,divider-clock>o @gpt10_gate_fckbti,composite-gate-clocko  @@F@gpt10_mux_fckbti,composite-mux-clock?o @@AFAgpt10_fckbti,composite-clock@Agpt11_gate_fckbti,composite-gate-clocko  @BFBgpt11_mux_fckbti,composite-mux-clock?o @@CFCgpt11_fckbti,composite-clockBCcore_96m_fckbfixed-factor-clockD@Fmmchs2_fckbti,wait-gate-clock o@Fmmchs1_fckbti,wait-gate-clock o@Fi2c3_fckbti,wait-gate-clock o@Fi2c2_fckbti,wait-gate-clock o@Fi2c1_fckbti,wait-gate-clock o@Fmcbsp5_gate_fckbti,composite-gate-clocko  @Fmcbsp1_gate_fckbti,composite-gate-clocko  @Fcore_48m_fckbfixed-factor-clock/@EFEmcspi4_fckbti,wait-gate-clockE o@Fmcspi3_fckbti,wait-gate-clockE o@Fmcspi2_fckbti,wait-gate-clockE o@Fmcspi1_fckbti,wait-gate-clockE o@Fuart2_fckbti,wait-gate-clockE o@Fuart1_fckbti,wait-gate-clockE o @Fcore_12m_fckbfixed-factor-clockF@GFGhdq_fckbti,wait-gate-clockG o@Fcore_l3_ickbfixed-factor-clock=@HFHsdrc_ickbti,wait-gate-clockH o@Fgpmc_fckbfixed-factor-clockHcore_l4_ickbfixed-factor-clock>@IFImmchs2_ickbti,omap3-interface-clockI o@Fmmchs1_ickbti,omap3-interface-clockI o@Fhdq_ickbti,omap3-interface-clockI o@Fmcspi4_ickbti,omap3-interface-clockI o@Fmcspi3_ickbti,omap3-interface-clockI o@Fmcspi2_ickbti,omap3-interface-clockI o@Fmcspi1_ickbti,omap3-interface-clockI o@Fi2c3_ickbti,omap3-interface-clockI o@Fi2c2_ickbti,omap3-interface-clockI o@Fi2c1_ickbti,omap3-interface-clockI o@Fuart2_ickbti,omap3-interface-clockI o@Fuart1_ickbti,omap3-interface-clockI o @Fgpt11_ickbti,omap3-interface-clockI o @Fgpt10_ickbti,omap3-interface-clockI o @Fmcbsp5_ickbti,omap3-interface-clockI o @Fmcbsp1_ickbti,omap3-interface-clockI o @Fomapctrl_ickbti,omap3-interface-clockI o@Fdss_tv_fckbti,gate-clock7o@Fdss_96m_fckbti,gate-clockDo@Fdss2_alwon_fckbti,gate-clocko@Fdummy_ckb fixed-clockgpt1_gate_fckbti,composite-gate-clocko @JFJgpt1_mux_fckbti,composite-mux-clock? @@KFKgpt1_fckbti,composite-clockJKaes2_ickbti,omap3-interface-clockIo @Fwkup_32k_fckbfixed-factor-clock?@LFLgpio1_dbckbti,gate-clockL o@Fsha12_ickbti,omap3-interface-clockI o@Fwdt2_fckbti,wait-gate-clockL o@Fwdt2_ickbti,omap3-interface-clockM o@Fwdt1_ickbti,omap3-interface-clockM o@Fgpio1_ickbti,omap3-interface-clockM o@Fomap_32ksync_ickbti,omap3-interface-clockM o@Fgpt12_ickbti,omap3-interface-clockM o@Fgpt1_ickbti,omap3-interface-clockM o@Fper_96m_fckbfixed-factor-clock(@ F per_48m_fckbfixed-factor-clock/@NFNuart3_fckbti,wait-gate-clockNo @Fgpt2_gate_fckbti,composite-gate-clocko@OFOgpt2_mux_fckbti,composite-mux-clock?@@PFPgpt2_fckbti,composite-clockOPgpt3_gate_fckbti,composite-gate-clocko@QFQgpt3_mux_fckbti,composite-mux-clock?o@@RFRgpt3_fckbti,composite-clockQRgpt4_gate_fckbti,composite-gate-clocko@SFSgpt4_mux_fckbti,composite-mux-clock?o@@TFTgpt4_fckbti,composite-clockSTgpt5_gate_fckbti,composite-gate-clocko@UFUgpt5_mux_fckbti,composite-mux-clock?o@@VFVgpt5_fckbti,composite-clockUVgpt6_gate_fckbti,composite-gate-clocko@WFWgpt6_mux_fckbti,composite-mux-clock?o@@XFXgpt6_fckbti,composite-clockWXgpt7_gate_fckbti,composite-gate-clocko@YFYgpt7_mux_fckbti,composite-mux-clock?o@@ZFZgpt7_fckbti,composite-clockYZgpt8_gate_fckbti,composite-gate-clocko @[F[gpt8_mux_fckbti,composite-mux-clock?o@@\F\gpt8_fckbti,composite-clock[\gpt9_gate_fckbti,composite-gate-clocko @]F]gpt9_mux_fckbti,composite-mux-clock?o@@^F^gpt9_fckbti,composite-clock]^per_32k_alwon_fckbfixed-factor-clock?@_F_gpio6_dbckbti,gate-clock_o@Fgpio5_dbckbti,gate-clock_o@Fgpio4_dbckbti,gate-clock_o@Fgpio3_dbckbti,gate-clock_o@Fgpio2_dbckbti,gate-clock_o @Fwdt3_fckbti,wait-gate-clock_o @Fper_l4_ickbfixed-factor-clock>@`F`gpio6_ickbti,omap3-interface-clock`o@Fgpio5_ickbti,omap3-interface-clock`o@Fgpio4_ickbti,omap3-interface-clock`o@Fgpio3_ickbti,omap3-interface-clock`o@Fgpio2_ickbti,omap3-interface-clock`o @Fwdt3_ickbti,omap3-interface-clock`o @Fuart3_ickbti,omap3-interface-clock`o @Fuart4_ickbti,omap3-interface-clock`o@Fgpt9_ickbti,omap3-interface-clock`o @Fgpt8_ickbti,omap3-interface-clock`o @Fgpt7_ickbti,omap3-interface-clock`o@Fgpt6_ickbti,omap3-interface-clock`o@Fgpt5_ickbti,omap3-interface-clock`o@Fgpt4_ickbti,omap3-interface-clock`o@Fgpt3_ickbti,omap3-interface-clock`o@Fgpt2_ickbti,omap3-interface-clock`o@Fmcbsp2_ickbti,omap3-interface-clock`o@Fmcbsp3_ickbti,omap3-interface-clock`o@Fmcbsp4_ickbti,omap3-interface-clock`o@Fmcbsp2_gate_fckbti,composite-gate-clocko@ F mcbsp3_gate_fckbti,composite-gate-clocko@ F mcbsp4_gate_fckbti,composite-gate-clocko@Femu_src_mux_ckb ti,mux-clockabc@@dFdemu_src_ckbti,clkdm-gate-clockd@eFepclk_fckbti,divider-clockeo@pclkx2_fckbti,divider-clockeo@atclk_fckbti,divider-clockeo@traceclk_src_fckb ti,mux-clockabco@@fFftraceclk_fckbti,divider-clockfo @secure_32k_fckb fixed-clock@gFggpt12_fckbfixed-factor-clockgwdt1_fckbfixed-factor-clockgsecurity_l4_ick2bfixed-factor-clock>@hFhaes1_ickbti,omap3-interface-clockho rng_ickbti,omap3-interface-clockh osha11_ickbti,omap3-interface-clockh odes1_ickbti,omap3-interface-clockh ocam_mclkbti,gate-clockiocam_ickb!ti,omap3-no-wait-interface-clock>o@Fcsi2_96m_fckbti,gate-clocko@Fsecurity_l3_ickbfixed-factor-clock=@jFjpka_ickbti,omap3-interface-clockj oicr_ickbti,omap3-interface-clockI odes2_ickbti,omap3-interface-clockI omspro_ickbti,omap3-interface-clockI omailboxes_ickbti,omap3-interface-clockI ossi_l4_ickbfixed-factor-clock>@qFqsr1_fckbti,wait-gate-clock osr2_fckbti,wait-gate-clock osr_l4_ickbfixed-factor-clock>dpll2_fckbti,divider-clock%o@@kFkdpll2_ckbti,omap3-dpll-clockk$@4,>F@lFldpll2_m2_ckbti,divider-clocklD@mFmiva2_ckbti,wait-gate-clockmo@Fmodem_fckbti,omap3-interface-clock o@Fsad2d_ickbti,omap3-interface-clock= o@Fmad2d_ickbti,omap3-interface-clock= o@Fmspro_fckbti,wait-gate-clock ossi_ssr_gate_fck_3430es2b ti,composite-no-wait-gate-clocko @nFnssi_ssr_div_fck_3430es2bti,composite-divider-clocko @$Z@oFossi_ssr_fck_3430es2bti,composite-clockno@pFpssi_sst_fck_3430es2bfixed-factor-clockp@Fhsotgusb_ick_3430es2b"ti,omap3-hsotgusb-interface-clockH o@Fssi_ick_3430es2bti,omap3-ssi-interface-clockq o@Fusim_gate_fckbti,composite-gate-clockDo  @|F|sys_d2_ckbfixed-factor-clock@sFsomap_96m_d2_fckbfixed-factor-clockD@tFtomap_96m_d4_fckbfixed-factor-clockD@uFuomap_96m_d8_fckbfixed-factor-clockD@vFvomap_96m_d10_fckbfixed-factor-clockD @wFwdpll5_m2_d4_ckbfixed-factor-clockr@xFxdpll5_m2_d8_ckbfixed-factor-clockr@yFydpll5_m2_d16_ckbfixed-factor-clockr@zFzdpll5_m2_d20_ckbfixed-factor-clockr@{F{usim_mux_fckbti,composite-mux-clock(stuvwxyz{o @@}F}usim_fckbti,composite-clock|}usim_ickbti,omap3-interface-clockM o @Fdpll5_ckbti,omap3-dpll-clock  $ L 4,>@~F~dpll5_m2_ckbti,divider-clock~ P@rFrsgx_gate_fckbti,composite-gate-clock%o @Fcore_d3_ckbfixed-factor-clock%@Fcore_d4_ckbfixed-factor-clock%@Fcore_d6_ckbfixed-factor-clock%@Fomap_192m_alwon_fckbfixed-factor-clock!@Fcore_d2_ckbfixed-factor-clock%@Fsgx_mux_fckbti,composite-mux-clock ) @@Fsgx_fckbti,composite-clocksgx_ickbti,wait-gate-clock= o@Fcpefuse_fckbti,gate-clock o@Fts_fckbti,gate-clock? o@Fusbtll_fckbti,wait-gate-clockr o@Fusbtll_ickbti,omap3-interface-clockI o@Fmmchs3_ickbti,omap3-interface-clockI o@Fmmchs3_fckbti,wait-gate-clock o@Fdss1_alwon_fck_3430es2bti,dss-gate-clocko@Fdss_ick_3430es2bti,omap3-dss-interface-clock>o@Fusbhost_120m_fckbti,gate-clockro@Fusbhost_48m_fckbti,dss-gate-clock/o@Fusbhost_ickbti,omap3-dss-interface-clock>o@Fuart4_fckbti,wait-gate-clockNo@Fclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainedpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainld2d_clkdmti,clockdomain dpll5_clkdmti,clockdomain~sgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH @Fdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH` fq ~`@Fpbias_regulatorti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-@Fgpio@48310000ti,omap3-gpioH1gpio1@Fgpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5@Fgpio@49058000ti,omap3-gpioI"gpio6@Fserial@4806a000ti,omap3-uartH HR|12txrxuart1lserial@4806c000ti,omap3-uartHIJ|34txrxuart2lserial@49020000ti,omap3-uartIJn|56txrxuart3ldefault!i2c@48070000 ti,omap3-i2cH8|txrxi2c1'@twl@48H& ti,twl4030default!rtcti,twl4030-rtc bciti,twl4030-bci +watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' @Fregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0@Fregulator-vmmc2ti,twl4030-vmmc2:0@Fregulator-vusb1v5ti,twl4030-vusb1v5@Fregulator-vusb1v8ti,twl4030-vusb1v8@Fregulator-vusb3v1ti,twl4030-vusb3v1@Fregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@9regulator-vsimti,twl4030-vsimw@-@Fgpioti,twl4030-gpioM@Ftwl4030-usbti,twl4030-usb Ygu@Fpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad8  7 Smadcti,twl4030-madcpower1ti,twl4030-power-omap3-evmti,twl4030-power-idlei2c@48072000 ti,omap3-i2cH 9|txrxi2c2i2c@48060000 ti,omap3-i2cH=|txrxi2c3tvp5146@5c ti,tvp5146m2\mailbox@48094000ti,omap3-mailboxmailboxH @dsp $ /spi@48098000ti,omap2-mcspiH Amcspi1:@|#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0 ti,tsc2046HB@Zen@w(& spi@4809a000ti,omap2-mcspiH Bmcspi2: |+,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [mcspi3: |tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi4:|FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1|=>txrxdefault!mmc@480b4000ti,omap3-hsmmcH @Vmmc2|/0txrxdefault!wlcore@2 ti,wl1271&/Immc@480ad000ti,omap3-hsmmcH ^mmc3|MNtxrx Cdisabledmmu@480bd400ti,omap2-iommuH mmu_ispJ@Fmmu@5d000000ti,omap2-iommu]mmu_iva Cdisabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@Zmpu ;< dcommontxrxtmcbsp1| txrx Cdisabledmcbsp@49022000ti,omap3-mcbspI I Zmpusidetone>?dcommontxrxsidetonetmcbsp2mcbsp2_sidetone|!"txrx Cdisabledmcbsp@49024000ti,omap3-mcbspI@I ZmpusidetoneYZdcommontxrxsidetonetmcbsp3mcbsp3_sidetone|txrx Cdisabledmcbsp@49026000ti,omap3-mcbspI`Zmpu 67 dcommontxrxtmcbsp4|txrx Cdisabledmcbsp@48096000ti,omap3-mcbspH `Zmpu QR dcommontxrxtmcbsp5|txrx Cdisabledsham@480c3000ti,omap3-shamshamH 0d1|Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hsohci@48064400ti,ohci-omap3HD&Lehci@48064800 ti,ehci-omapHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcn ,ethernet@gpmcsmsc,lan9221smsc,lan9115+9K]l(--xK.KH`w& default!nand@0,0hynix,h8kds0un0mer-4em bch8+9,K,]l",(6@RR(wpartition@0 !X-Loaderpartition@0x80000!U-Bootpartition@0x1c0000 !Environment$partition@0x280000!Kernel(Ppartition@0x780000 !Filesystemxusb_otg_hs@480ab000ti,omap3-musbH \]dmcdma usb_otg_hs'2: CRZ _usb2-phyi2dss@48050000 ti,omap3-dssHCok dss_corefckdefault!dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H Zprotophypll Cdisabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH Cdisabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  Cdisabled dss_vencfcktv_dac_clkportendpointo@Fssi-controller@48058000 ti,omap3-ssissiCokHHZsysgddGdgdd_mpu p ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHZtxrx&CDssi-port@4805b000ti,omap3-ssi-portHHZtxrx&EFserial@49042000ti,omap3-uartI P|QRtxrxuart4lregulator-abb-mpu ti,abb-v1 abb_mpu_ivaH0rH0hZbase-addressint-address`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\#isp@480bc000 ti,omap3-ispH H bportsregulator-vddvarioregulator-fixed vddvario9@Fregulator-vdd33aregulator-fixedvdd33a9@Fleds gpio-ledsledb!omap3evm::ledb  default-onwl12xx_vmmcregulator-fixedvwl1271w@w@  p  1default!@Fbacklightgpio-backlight < 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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pins#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xylinux,wakeuppendown-gpioti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removablecap-power-off-cardref-clock-frequencystatusti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerremote-endpointdata-lines#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typegpioslinux,default-triggerstartup-delay-usenable-active-highvin-supplydefault-onenable-active-lowpower-supplyenable-gpiosreset-gpiosmode-gpios