8( Lti,omap3-evm-37xxti,omap36xx&7TI OMAP37XX EVM (TMDSEVM3730)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000 l/displaymemoryumemorycpuscpu@0arm,cortex-a8ucpucpus 'O 57pmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-bush l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-bus  pinmux@30 ti,omap3-padconfpinctrl-single08#@Fpinmux_twl4030_pinsNA@Fpinmux_dss_dpi_pins2N@Fpinmux_mmc1_pinsPN "$&@Fpinmux_mmc2_pins0N(*,.A02@Fpinmux_uart3_pinsNnAp@Fpinmux_wl12xx_gpioNPN@Fpinmux_smsc911x_pinsN@Fscm_conf@270sysconsimple-busp0 p0@Fpbias_regulatorti,pbias-omap3ti,pbias-omapbpbias_mmc_omap2430ipbias_mmc_omap2430xw@-@Fclocksmcbsp5_mux_fckti,composite-mux-clockh@Fmcbsp5_fckti,composite-clockmcbsp1_mux_fckti,composite-mux-clock@ F mcbsp1_fckti,composite-clock mcbsp2_mux_fckti,composite-mux-clock @ F mcbsp2_fckti,composite-clock mcbsp3_mux_fckti,composite-mux-clock h@Fmcbsp3_fckti,composite-clockmcbsp4_mux_fckti,composite-mux-clock h@Fmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \#pinmux_twl4030_vpins N@Fpinmux_dss_dpi_pins10N  @Faes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocksvirt_16_8m_ck fixed-clockY@Fosc_sys_ck ti,mux-clock @@Fsys_ckti,divider-clockp@Fsys_clkout1ti,gate-clock pdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clock@Fdpll4_x2_ckfixed-factor-clockcorex2_fckfixed-factor-clock@Fwkup_l4_ickfixed-factor-clock@NFNcorex2_d3_fckfixed-factor-clock@Fcorex2_d5_fckfixed-factor-clock@Fclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock@@F@virt_12m_ck fixed-clock@Fvirt_13m_ck fixed-clock]@@Fvirt_19200000_ck fixed-clock$@Fvirt_26000000_ck fixed-clock@Fvirt_38_4m_ck fixed-clockI@Fdpll4_ckti,omap3-dpll-per-j-type-clock D 0@Fdpll4_m2_ckti,divider-clock? H@ F dpll4_m2x2_mul_ckfixed-factor-clock @!F!dpll4_m2x2_ckti,hsdiv-gate-clock! @"F"omap_96m_alwon_fckfixed-factor-clock"@)F)dpll3_ckti,omap3-dpll-core-clock @ 0@Fdpll3_m3_ckti,divider-clock@@#F#dpll3_m3x2_mul_ckfixed-factor-clock#@$F$dpll3_m3x2_ckti,hsdiv-gate-clock$  @%F%emu_core_alwon_ckfixed-factor-clock%@bFbsys_altclk fixed-clock@.F.mcbsp_clks fixed-clock@Fdpll3_m2_ckti,divider-clock @@Fcore_ckfixed-factor-clock@&F&dpll1_fckti,divider-clock& @@'F'dpll1_ckti,omap3-dpll-clock'  $ @ 4@Fdpll1_x2_ckfixed-factor-clock@(F(dpll1_x2m2_ckti,divider-clock( D@<F<cm_96m_fckfixed-factor-clock)@*F*omap_96m_fck ti,mux-clock* @@EFEdpll4_m3_ckti,divider-clock @@+F+dpll4_m3x2_mul_ckfixed-factor-clock+@,F,dpll4_m3x2_ckti,hsdiv-gate-clock, @-F-omap_54m_fck ti,mux-clock-. @@8F8cm_96m_d2_fckfixed-factor-clock*@/F/omap_48m_fck ti,mux-clock/. @@0F0omap_12m_fckfixed-factor-clock0@GFGdpll4_m4_ckti,divider-clock @@1F1dpll4_m4x2_mul_ckti,fixed-factor-clock1.<I@2F2dpll4_m4x2_ckti,gate-clock2 I@Fdpll4_m5_ckti,divider-clock?@@3F3dpll4_m5x2_mul_ckti,fixed-factor-clock3.<I@4F4dpll4_m5x2_ckti,hsdiv-gate-clock4 I@jFjdpll4_m6_ckti,divider-clock?@@5F5dpll4_m6x2_mul_ckfixed-factor-clock5@6F6dpll4_m6x2_ckti,hsdiv-gate-clock6 @7F7emu_per_alwon_ckfixed-factor-clock7@cFcclkout2_src_gate_ck ti,composite-no-wait-gate-clock& p@9F9clkout2_src_mux_ckti,composite-mux-clock&*8 p@:F:clkout2_src_ckti,composite-clock9:@;F;sys_clkout2ti,divider-clock;@ p\mpu_ckfixed-factor-clock<@=F=arm_fckti,divider-clock= $emu_mpu_alwon_ckfixed-factor-clock=@dFdl3_ickti,divider-clock& @@>F>l4_ickti,divider-clock> @@?F?rm_ickti,divider-clock? @gpt10_gate_fckti,composite-gate-clock  @AFAgpt10_mux_fckti,composite-mux-clock@ @@BFBgpt10_fckti,composite-clockABgpt11_gate_fckti,composite-gate-clock  @CFCgpt11_mux_fckti,composite-mux-clock@ @@DFDgpt11_fckti,composite-clockCDcore_96m_fckfixed-factor-clockE@Fmmchs2_fckti,wait-gate-clock @Fmmchs1_fckti,wait-gate-clock @Fi2c3_fckti,wait-gate-clock @Fi2c2_fckti,wait-gate-clock @Fi2c1_fckti,wait-gate-clock @Fmcbsp5_gate_fckti,composite-gate-clock  @Fmcbsp1_gate_fckti,composite-gate-clock  @ F core_48m_fckfixed-factor-clock0@FFFmcspi4_fckti,wait-gate-clockF @Fmcspi3_fckti,wait-gate-clockF @Fmcspi2_fckti,wait-gate-clockF @Fmcspi1_fckti,wait-gate-clockF @Fuart2_fckti,wait-gate-clockF @Fuart1_fckti,wait-gate-clockF  @Fcore_12m_fckfixed-factor-clockG@HFHhdq_fckti,wait-gate-clockH @Fcore_l3_ickfixed-factor-clock>@IFIsdrc_ickti,wait-gate-clockI @Fgpmc_fckfixed-factor-clockIcore_l4_ickfixed-factor-clock?@JFJmmchs2_ickti,omap3-interface-clockJ @Fmmchs1_ickti,omap3-interface-clockJ @Fhdq_ickti,omap3-interface-clockJ @Fmcspi4_ickti,omap3-interface-clockJ @Fmcspi3_ickti,omap3-interface-clockJ @Fmcspi2_ickti,omap3-interface-clockJ @Fmcspi1_ickti,omap3-interface-clockJ @Fi2c3_ickti,omap3-interface-clockJ @Fi2c2_ickti,omap3-interface-clockJ @Fi2c1_ickti,omap3-interface-clockJ @Fuart2_ickti,omap3-interface-clockJ @Fuart1_ickti,omap3-interface-clockJ  @Fgpt11_ickti,omap3-interface-clockJ  @Fgpt10_ickti,omap3-interface-clockJ  @Fmcbsp5_ickti,omap3-interface-clockJ  @Fmcbsp1_ickti,omap3-interface-clockJ  @Fomapctrl_ickti,omap3-interface-clockJ @Fdss_tv_fckti,gate-clock8@Fdss_96m_fckti,gate-clockE@Fdss2_alwon_fckti,gate-clock@Fdummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock @KFKgpt1_mux_fckti,composite-mux-clock@ @@LFLgpt1_fckti,composite-clockKLaes2_ickti,omap3-interface-clockJ @Fwkup_32k_fckfixed-factor-clock@@MFMgpio1_dbckti,gate-clockM @Fsha12_ickti,omap3-interface-clockJ @Fwdt2_fckti,wait-gate-clockM @Fwdt2_ickti,omap3-interface-clockN @Fwdt1_ickti,omap3-interface-clockN @Fgpio1_ickti,omap3-interface-clockN @Fomap_32ksync_ickti,omap3-interface-clockN @Fgpt12_ickti,omap3-interface-clockN @Fgpt1_ickti,omap3-interface-clockN @Fper_96m_fckfixed-factor-clock)@ F per_48m_fckfixed-factor-clock0@OFOuart3_fckti,wait-gate-clockO @Fgpt2_gate_fckti,composite-gate-clock@PFPgpt2_mux_fckti,composite-mux-clock@@@QFQgpt2_fckti,composite-clockPQgpt3_gate_fckti,composite-gate-clock@RFRgpt3_mux_fckti,composite-mux-clock@@@SFSgpt3_fckti,composite-clockRSgpt4_gate_fckti,composite-gate-clock@TFTgpt4_mux_fckti,composite-mux-clock@@@UFUgpt4_fckti,composite-clockTUgpt5_gate_fckti,composite-gate-clock@VFVgpt5_mux_fckti,composite-mux-clock@@@WFWgpt5_fckti,composite-clockVWgpt6_gate_fckti,composite-gate-clock@XFXgpt6_mux_fckti,composite-mux-clock@@@YFYgpt6_fckti,composite-clockXYgpt7_gate_fckti,composite-gate-clock@ZFZgpt7_mux_fckti,composite-mux-clock@@@[F[gpt7_fckti,composite-clockZ[gpt8_gate_fckti,composite-gate-clock @\F\gpt8_mux_fckti,composite-mux-clock@@@]F]gpt8_fckti,composite-clock\]gpt9_gate_fckti,composite-gate-clock @^F^gpt9_mux_fckti,composite-mux-clock@@@_F_gpt9_fckti,composite-clock^_per_32k_alwon_fckfixed-factor-clock@@`F`gpio6_dbckti,gate-clock`@Fgpio5_dbckti,gate-clock`@Fgpio4_dbckti,gate-clock`@Fgpio3_dbckti,gate-clock`@Fgpio2_dbckti,gate-clock` @Fwdt3_fckti,wait-gate-clock` @Fper_l4_ickfixed-factor-clock?@aFagpio6_ickti,omap3-interface-clocka@Fgpio5_ickti,omap3-interface-clocka@Fgpio4_ickti,omap3-interface-clocka@Fgpio3_ickti,omap3-interface-clocka@Fgpio2_ickti,omap3-interface-clocka @Fwdt3_ickti,omap3-interface-clocka @Fuart3_ickti,omap3-interface-clocka @Fuart4_ickti,omap3-interface-clocka@Fgpt9_ickti,omap3-interface-clocka @Fgpt8_ickti,omap3-interface-clocka @Fgpt7_ickti,omap3-interface-clocka@Fgpt6_ickti,omap3-interface-clocka@Fgpt5_ickti,omap3-interface-clocka@Fgpt4_ickti,omap3-interface-clocka@Fgpt3_ickti,omap3-interface-clocka@Fgpt2_ickti,omap3-interface-clocka@Fmcbsp2_ickti,omap3-interface-clocka@Fmcbsp3_ickti,omap3-interface-clocka@Fmcbsp4_ickti,omap3-interface-clocka@Fmcbsp2_gate_fckti,composite-gate-clock@ F mcbsp3_gate_fckti,composite-gate-clock@Fmcbsp4_gate_fckti,composite-gate-clock@Femu_src_mux_ck ti,mux-clockbcd@@eFeemu_src_ckti,clkdm-gate-clocke@fFfpclk_fckti,divider-clockf@pclkx2_fckti,divider-clockf@atclk_fckti,divider-clockf@traceclk_src_fck ti,mux-clockbcd@@gFgtraceclk_fckti,divider-clockg @secure_32k_fck fixed-clock@hFhgpt12_fckfixed-factor-clockhwdt1_fckfixed-factor-clockhsecurity_l4_ick2fixed-factor-clock?@iFiaes1_ickti,omap3-interface-clocki rng_ickti,omap3-interface-clocki sha11_ickti,omap3-interface-clocki des1_ickti,omap3-interface-clocki cam_mclkti,gate-clockjIcam_ick!ti,omap3-no-wait-interface-clock?@Fcsi2_96m_fckti,gate-clock@Fsecurity_l3_ickfixed-factor-clock>@kFkpka_ickti,omap3-interface-clockk icr_ickti,omap3-interface-clockJ des2_ickti,omap3-interface-clockJ mspro_ickti,omap3-interface-clockJ mailboxes_ickti,omap3-interface-clockJ ssi_l4_ickfixed-factor-clock?@rFrsr1_fckti,wait-gate-clock sr2_fckti,wait-gate-clock sr_l4_ickfixed-factor-clock?dpll2_fckti,divider-clock&@@lFldpll2_ckti,omap3-dpll-clockl$@4r@mFmdpll2_m2_ckti,divider-clockmD@nFniva2_ckti,wait-gate-clockn@Fmodem_fckti,omap3-interface-clock @Fsad2d_ickti,omap3-interface-clock> @Fmad2d_ickti,omap3-interface-clock> @Fmspro_fckti,wait-gate-clock ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock @oFossi_ssr_div_fck_3430es2ti,composite-divider-clock @$@pFpssi_ssr_fck_3430es2ti,composite-clockop@qFqssi_sst_fck_3430es2fixed-factor-clockq@Fhsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clockI @Fssi_ick_3430es2ti,omap3-ssi-interface-clockr @Fusim_gate_fckti,composite-gate-clockE  @}F}sys_d2_ckfixed-factor-clock@tFtomap_96m_d2_fckfixed-factor-clockE@uFuomap_96m_d4_fckfixed-factor-clockE@vFvomap_96m_d8_fckfixed-factor-clockE@wFwomap_96m_d10_fckfixed-factor-clockE @xFxdpll5_m2_d4_ckfixed-factor-clocks@yFydpll5_m2_d8_ckfixed-factor-clocks@zFzdpll5_m2_d16_ckfixed-factor-clocks@{F{dpll5_m2_d20_ckfixed-factor-clocks@|F|usim_mux_fckti,composite-mux-clock(tuvwxyz{| @@~F~usim_fckti,composite-clock}~usim_ickti,omap3-interface-clockN  @Fdpll5_ckti,omap3-dpll-clock  $ L 4r@Fdpll5_m2_ckti,divider-clock P@sFssgx_gate_fckti,composite-gate-clock& @Fcore_d3_ckfixed-factor-clock&@Fcore_d4_ckfixed-factor-clock&@Fcore_d6_ckfixed-factor-clock&@Fomap_192m_alwon_fckfixed-factor-clock"@Fcore_d2_ckfixed-factor-clock&@Fsgx_mux_fckti,composite-mux-clock * @@Fsgx_fckti,composite-clocksgx_ickti,wait-gate-clock> @Fcpefuse_fckti,gate-clock @Fts_fckti,gate-clock@ @Fusbtll_fckti,wait-gate-clocks @Fusbtll_ickti,omap3-interface-clockJ @Fmmchs3_ickti,omap3-interface-clockJ @Fmmchs3_fckti,wait-gate-clock @Fdss1_alwon_fck_3430es2ti,dss-gate-clockI@Fdss_ick_3430es2ti,omap3-dss-interface-clock?@Fusbhost_120m_fckti,gate-clocks@Fusbhost_48m_fckti,dss-gate-clock0@Fusbhost_ickti,omap3-dss-interface-clock?@Fuart4_fckti,wait-gate-clockO@Fclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainfdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainmd2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH @Fdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `@Fgpio@48310000ti,omap3-gpioH1gpio1@Fgpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5@Fgpio@49058000ti,omap3-gpioI"gpio6@Fserial@4806a000ti,omap3-uartH HR12txrxuart1lserial@4806c000ti,omap3-uartHIJ34txrxuart2lserial@49020000ti,omap3-uartIJn56txrxuart3ldefault!i2c@48070000 ti,omap3-i2cH8txrxi2c1'@twl@48H& ti,twl4030default!rtcti,twl4030-rtc bciti,twl4030-bci +watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1x ' @Fregulator-vdacti,twl4030-vdacxw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1x:0@Fregulator-vmmc2ti,twl4030-vmmc2x:0@Fregulator-vusb1v5ti,twl4030-vusb1v5@Fregulator-vusb1v8ti,twl4030-vusb1v8@Fregulator-vusb3v1ti,twl4030-vusb3v1@Fregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2xw@w@9regulator-vsimti,twl4030-vsimxw@-@Fgpioti,twl4030-gpioM@Ftwl4030-usbti,twl4030-usb Ygu@Fpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad8  7 Smadcti,twl4030-madcpower1ti,twl4030-power-omap3-evmti,twl4030-power-idlei2c@48072000 ti,omap3-i2cH 9txrxi2c2i2c@48060000 ti,omap3-i2cH=txrxi2c3tvp5146@5c ti,tvp5146m2\mailbox@48094000ti,omap3-mailboxmailboxH @dsp $ /spi@48098000ti,omap2-mcspiH Amcspi1:@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0 ti,tsc2046HB@Zen@w(& spi@4809a000ti,omap2-mcspiH Bmcspi2: +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [mcspi3: tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi4:FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrxSdefault!mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxdefault!wlcore@2 ti,wl1271&/Immc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx Cdisabledmmu@480bd400Jti,omap2-iommuH mmu_ispW@Fmmu@5d000000Jti,omap2-iommu]mmu_iva Cdisabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@gmpu ;< qcommontxrxmcbsp1 txrx Cdisabledmcbsp@49022000ti,omap3-mcbspI I gmpusidetone>?qcommontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx Cdisabledmcbsp@49024000ti,omap3-mcbspI@I gmpusidetoneYZqcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx Cdisabledmcbsp@49026000ti,omap3-mcbspI`gmpu 67 qcommontxrxmcbsp4txrx Cdisabledmcbsp@48096000ti,omap3-mcbspH `gmpu QR qcommontxrxmcbsp5txrx Cdisabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N 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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xylinux,wakeuppendown-gpioti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removablecap-power-off-cardref-clock-frequencystatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerremote-endpointdata-lines#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typegpioslinux,default-triggerstartup-delay-usenable-active-highvin-supplydefault-onenable-active-lowpower-supplyenable-gpiosreset-gpiosmode-gpios